| /linux/tools/perf/pmu-events/arch/powerpc/power10/ |
| H A D | datasource.json | 15 …"BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local cor…
20 …"BriefDescription": "The processor's L1 data cache was reloaded from beyond the local core's L3 du…
30 …"BriefDescription": "The processor's data cache was reloaded from local, remote, or distant memory…
60 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
65 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
70 …"BriefDescription": "The processor's instruction cache was reloaded from the local core's L2 due t…
75 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a …
80 …"BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local…
85 …"BriefDescription": "The processor's L1 data cache was reloaded from a source beyond the local cor…
90 …"BriefDescription": "The processor's instruction cache was reloaded from a source beyond the local…
[all …]
|
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-class-remoteproc | 4 Description: Remote processor firmware
7 remote processor.
9 To change the running firmware, ensure the remote processor is
15 Description: Remote processor state
17 Reports the state of the remote processor, which will be one of:
25 "offline" means the remote processor is powered off.
27 "suspended" means that the remote processor is suspended and
30 "running" is the normal state of an available remote processor
33 the remote processor.
35 "invalid" is returned if the remote processor is in an
[all …]
|
| /linux/arch/sh/ |
| H A D | Kconfig | 78 The SuperH is a RISC processor targeted for use in embedded systems
152 # Processor families
214 prompt "Processor sub-type selection"
217 # Processor subtypes
220 # SH-2 Processor Support
223 bool "Support SH7619 processor"
228 bool "Support J2 processor"
233 # SH-2A Processor Support
236 bool "Support SH7201 processor"
242 bool "Support SH7203 processor"
[all …]
|
| /linux/tools/perf/pmu-events/arch/powerpc/power8/ |
| H A D | cache.json | 5 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
6 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
11 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
12 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand …
24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
35 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
36 …"PublicDescription": "The processor's data cache was reloaded from a location other than the local…
[all …]
|
| H A D | frontend.json | 89 …"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from an…
90 …"PublicDescription": "The processor's Instruction cache was reloaded with Modified (M) data from a…
95 …"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from anot…
96 …"PublicDescription": "The processor's Instruction cache was reloaded with Shared (S) data from ano…
101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…
102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…
107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …
108 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on…
113 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an…
114 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to e…
[all …]
|
| H A D | other.json | 371 …"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another c…
372 …"PublicDescription": "The processor's data cache was reloaded with Modified (M) data from another …
377 …"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chi…
378 …"PublicDescription": "The processor's data cache was reloaded with Shared (S) data from another ch…
383 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
384 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
389 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
390 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…
395 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to either de…
396 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o…
[all …]
|
| /linux/drivers/eisa/ |
| H A D | eisa.ids | 74 AIR1001 "AIR P6NDP PCI/EISA Dual-Pentium Processor System Board"
84 ALR3000 "80486 Processor Module"
85 ALR3010 "Pentium Processor Board"
91 ALRB0A0 "Primary System Processor Board - 80486DX2/66"
92 ALRB0B0 "Secondary System Processor Board - 80486DX2/66"
245 CPQ5000 "Compaq 386/33 System Processor Board used as Secondary"
246 CPQ5251 "Compaq 5/133 System Processor Board-2MB"
247 CPQ5253 "Compaq 5/166 System Processor Board-2MB"
248 CPQ5255 "Compaq 5/133 System Processor Board-1MB"
249 CPQ525D "Compaq 5/100 System Processor Board-1MB"
[all …]
|
| /linux/arch/arm/mach-imx/ |
| H A D | Kconfig | 47 This enables support for Freescale i.MX31 processor
53 This enables support for Freescale i.MX35 processor
64 This enables support for Freescale i.MX1 processor
75 This enables support for Freescale i.MX25 processor
82 This enables support for Freescale i.MX27 processor
100 This enables support for Freescale i.MX50 processor.
106 This enables support for Freescale i.MX51 processor
113 This enables support for Freescale i.MX53 processor.
136 This enables support for Freescale i.MX6 Quad processor.
145 This enables support for Freescale i.MX6 SoloLite processor.
[all …]
|
| /linux/Documentation/arch/powerpc/ |
| H A D | elf_hwcaps.rst | 80 The processor is PowerPC 601.
93 The processor is 40x or 44x family.
97 The processor has a unified L1 cache for instructions and data, as
99 Unused in the kernel since 39c8bf2b3cc1 ("powerpc: Retire e200 core (mpc555x processor)")
112 This is a 601 specific HWCAP, so if it is known that the processor
118 The processor is POWER4 or PPC970/FX/MP.
122 The processor is POWER5.
125 The processor is POWER5+.
128 The processor is Cell.
131 The processor implements the embedded category ("BookE") architecture.
[all …]
|
| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,omap-remoteproc.yaml | 13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
22 sub-system. The DSP processor sub-system can contain any of the TI's C64x,
23 C66x or C67x family of DSP cores as the main execution unit. The IPU processor
27 Each remote processor sub-system is represented as a single DT node. Each node
29 the host processor (MPU) to perform the device management of the remote
30 processor and to communicate with the remote processor. The various properties
54 for this remote processor to access any external RAM memory or
[all …]
|
| /linux/Documentation/devicetree/bindings/soc/qcom/ |
| H A D | qcom,smsm.yaml | 16 information between the processors in a Qualcomm SoC. Each processor is
17 assigned 32 bits of state that can be modified. A processor can through a
19 certain bit owned by a certain remote processor.
32 Identifier of the local processor in the list of hosts, or in other words
34 processor.
41 this client. Each entry represents the N:th remote processor by index
57 remote processor.
63 Each processor's state bits are described by a subnode of the SMSM device
65 remote processor's state bits or the local processors bits. The node
75 belong to a remote processor.
[all …]
|
| /linux/Documentation/admin-guide/pm/ |
| H A D | intel_idle.rst | 20 a particular processor model in it depends on whether or not it recognizes that
21 processor model and may also depend on information coming from the platform
26 ``intel_idle`` uses the ``MWAIT`` instruction to inform the processor that the
28 processor's functional blocks into low-power states. That instruction takes two
30 first of which, referred to as a *hint*, can be used by the processor to
68 Each ``MWAIT`` hint value is interpreted by the processor as a license to
69 reconfigure itself in a certain way in order to save energy. The processor
73 processor) corresponding to them depends on the processor model and it may also
80 for different processor models included in the driver itself and the ACPI tables
81 of the system. The former are always used if the processor model at hand is
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/goldmont/ |
| H A D | cache.json | 72 …processor) in the system, one of those caching agents indicated that they had a dirty copy of the …
239 …demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data for…
245 …demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, data for…
250 …demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data …
256 …demand & prefetch) that miss the L2 cache with a snoop hit in the other processor module, no data …
261 …mand & prefetch) that true miss for the L2 cache with a snoop miss in the other processor module.",
267 …refetch) that true miss for the L2 cache with a snoop miss in the other processor module. Require…
294 … or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data for…
300 … or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, data for…
305 … or L2 prefetchers that miss the L2 cache with a snoop hit in the other processor module, no data …
[all …]
|
| /linux/arch/arm/include/asm/ |
| H A D | proc-fns.h | 23 struct processor { struct
33 * Set up any processor specifics argument
37 * Check for processor bugs argument
41 * Disable any processor specifics argument
49 * Idle the processor argument
53 * Processor architecture specific
82 static inline void init_proc_vtable(const struct processor *p) in init_proc_vtable() argument
103 extern struct processor processor;
113 extern struct processor *cpu_vtable[];
116 static inline void init_proc_vtable(const struct processor *p) in init_proc_vtable()
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | data-fabric.json | 4 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 0.",
12 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 1.",
20 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 2.",
28 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 3.",
36 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 4.",
44 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 5.",
52 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 6.",
60 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 7.",
68 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 8.",
76 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 9.",
[all …]
|
| /linux/Documentation/staging/ |
| H A D | remoteproc.rst | 2 Remote Processor Framework
8 Modern SoCs typically have heterogeneous remote processor devices in asymmetric
29 existing virtio drivers with remote processor backends at a minimal development
39 Boot a remote processor (i.e. load its firmware, power it on, ...).
41 If the remote processor is already powered on, this function immediately
54 Power off a remote processor (previously booted with rproc_boot()).
76 the remote processor's refcount, so always use rproc_put() to
91 /* let's power on and boot our remote processor */
100 * our remote processor is now powered on... give it some work
116 Allocate a new remote processor handle, but don't register
[all …]
|
| /linux/include/linux/soc/apple/ |
| H A D | rtkit.h | 24 * @is_mapped: Shared memory buffer is managed by the co-processor.
40 * @crashed: Called when the co-processor has crashed. Runs in process
50 * buffer is managed by the co-processor and needs to be mapped.
74 * @mbox_name: mailbox name used to communicate with the co-processor
76 * @ops: pointer to rtkit_ops to be used for this co-processor
88 * @mbox_name: mailbox name used to communicate with the co-processor
90 * @ops: pointer to rtkit_ops to be used for this co-processor
102 * Reinitialize internal structures. Must only be called with the co-processor
109 * co-processor has been started.
114 * Quiesce the co-processor.
[all …]
|
| /linux/drivers/acpi/ |
| H A D | acpi_processor.c | 3 * acpi_processor.c - ACPI processor enumeration support
23 #include <acpi/processor.h>
179 /* Check presence of Processor Clocking Control by searching for \_SB.PCCH. */
212 "BIOS reported wrong ACPI id %d for the processor\n", in acpi_processor_set_per_cpu()
250 /* Leave the processor device array in place to detect buggy bios */ in acpi_processor_hotadd_init()
300 /* Declared with "Processor" statement; match ProcessorID */ in acpi_processor_get_info()
304 "Failed to evaluate processor object (0x%x)\n", in acpi_processor_get_info()
309 pr->acpi_id = object.processor.proc_id; in acpi_processor_get_info()
318 "Failed to evaluate processor _UID (0x%x)\n", in acpi_processor_get_info()
332 "Failed to get unique processor _UID (0x%x)\n", in acpi_processor_get_info()
[all …]
|
| /linux/tools/power/cpupower/man/ |
| H A D | cpupower-monitor.1 | 3 cpupower\-monitor \- Report processor frequency and idle statistics
18 \fBcpupower-monitor \fP reports processor topology, frequency and idle power
22 \fBcpupower-monitor \fP implements independent processor sleep state and
42 The name and a description of each counter and its processor hierarchy level
50 [P] \-> Processor Package (Socket)
101 state it is also used to show C0 (processor is active) and Cx (processor is in
117 For example an IvyBridge processor has sleep state capabilities which got
118 introduced in Nehalem and SandyBridge processor families.
119 Thus on an IvyBridge processor one will get Nehalem and SandyBridge sleep
125 AMD laptop and desktop processor (family 12h and 14h) sleep state counters.
[all …]
|
| /linux/Documentation/hwmon/ |
| H A D | asc7621.rst | 117 - Monitors VCCP, 2.5V, 3.3V, 5.0V, and 12V motherboard/processor supplies
137 peci_legacy = 1, PECI Processor Temperature 0
141 4 PECI Processor Temperature 0
142 5 PECI Processor Temperature 1
143 6 PECI Processor Temperature 2
144 7 PECI Processor Temperature 3
153 4 PECI Processor Temperature 0
154 5 PECI Processor Temperature 1
155 6 PECI Processor Temperature 2
156 7 PECI Processor Temperature 3
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/ivybridge/ |
| H A D | uncore-cache.json | 147 … "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
156 "BriefDescription": "An external snoop hits a modified line in some processor core.",
165 …re snoop initiated by this Cbox due to processor core memory request which hits a modified line in…
174 …cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
183 "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
192 … snoop initiated by this Cbox due to processor core memory request which hits a non-modified line …
201 …fDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
210 "BriefDescription": "An external snoop misses in some processor core.",
219 …ross-core snoop initiated by this Cbox due to processor core memory request which misses in some p…
|
| /linux/tools/perf/pmu-events/arch/x86/sandybridge/ |
| H A D | uncore-cache.json | 147 … "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
156 "BriefDescription": "An external snoop hits a modified line in some processor core.",
165 …re snoop initiated by this Cbox due to processor core memory request which hits a modified line in…
174 …cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
183 "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
192 … snoop initiated by this Cbox due to processor core memory request which hits a non-modified line …
201 …fDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
210 "BriefDescription": "An external snoop misses in some processor core.",
219 …ross-core snoop initiated by this Cbox due to processor core memory request which misses in some p…
|
| /linux/tools/perf/pmu-events/arch/x86/goldmontplus/ |
| H A D | cache.json | 72 …processor) in the system, one of those caching agents indicated that they had a dirty copy of the …
239 …ads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
245 …ads (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
250 …s (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
256 …d & prefetch) true miss for the L2 cache with a snoop miss in the other processor module. Require…
294 …by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data for…
300 …by L1 or L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data for…
305 … L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.",
311 …2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module. Require…
349 …sts (demand & prefetch) miss the L2 cache with a snoop hit in the other processor module, data for…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | pipeline.json | 8 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
17 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
27 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
37 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
47 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
57 …s retired. Branch prediction predicts the branch target and enables the processor to begin executi…
67 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
77 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
87 … retired. Branch prediction predicts the branch target and enables the processor to begin executi…
97 …s retired. Branch prediction predicts the branch target and enables the processor to begin executi…
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/haswell/ |
| H A D | uncore-cache.json | 147 … "A cross-core snoop resulted from L3 Eviction which hits a modified line in some processor core.",
156 "BriefDescription": "An external snoop hits a modified line in some processor core.",
165 …re snoop initiated by this Cbox due to processor core memory request which hits a modified line in…
174 …cross-core snoop resulted from L3 Eviction which hits a non-modified line in some processor core.",
183 "BriefDescription": "An external snoop hits a non-modified line in some processor core.",
192 … snoop initiated by this Cbox due to processor core memory request which hits a non-modified line …
201 …fDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
210 "BriefDescription": "An external snoop misses in some processor core.",
219 …ross-core snoop initiated by this Cbox due to processor core memory request which misses in some p…
|