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/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-fm-tx.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _fm-tx-controls:
15 .. _fm-tx-control-id:
27 step are driver-specific.
34 to 31 pre-defined programme types.
52 programme-related information or any other text. In these cases,
103 receiver-generated distortion and prevent overmodulation.
107 useconds. Step and range are driver-specific.
111 are driver-specific.
121 range and step are driver-specific.
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H A Dext-ctrls-fm-rx.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _fm-rx-controls:
13 .. _fm-rx-control-id:
27 Gets RDS Programme Type field. This encodes up to 31 pre-defined
45 wishes to transmit longer PS names, programme-related information or
70 enum v4l2_deemphasis -
71 Configures the de-emphasis value for reception. A de-emphasis filter
75 values for de-emphasis. Here they are:
79 .. flat-table::
80 :header-rows: 0
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dtoshiba,tc358767.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrey Gusakov <andrey.gusakov@cogentembedded.com>
19 - items:
20 - enum:
21 - toshiba,tc358867
22 - toshiba,tc9595
23 - const: toshiba,tc358767
24 - const: toshiba,tc358767
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H A Danalogix,anx7625.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Xin Ji <xji@analogixsemi.com>
14 The ANX7625 is an ultra-low power 4K Mobile HD Transmitter
28 enable-gpios:
32 reset-gpios:
36 vdd10-supply:
39 vdd18-supply:
42 vdd33-supply:
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/linux/Documentation/devicetree/bindings/phy/
H A Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
19 Two set of 3-tuple setting for each (up to 3)
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
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H A Dqcom,qusb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Wesley Cheng <quic_wcheng@quicinc.com>
19 - items:
20 - enum:
21 - qcom,ipq6018-qusb2-phy
22 - qcom,ipq8074-qusb2-phy
23 - qcom,ipq9574-qusb2-phy
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H A Dqcom,snps-eusb2-repeater.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-repeater.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abel Vesa <abel.vesa@linaro.org>
19 - items:
20 - enum:
21 - qcom,pm7550ba-eusb2-repeater
22 - const: qcom,pm8550b-eusb2-repeater
23 - enum:
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H A Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy(@[0-9a-f]+)?$"
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H A Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
42 "#address-cells":
45 "#size-cells":
48 vdda1v1-supply:
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/linux/include/linux/phy/
H A Dphy-dp.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct phy_configure_opts_dp - DisplayPort PHY configuration set
52 * @pre:
54 * Pre-emphasis levels, as specified by DisplayPort specification, to be
59 unsigned int pre[4]; member
64 * Flag indicating, whether or not to enable spread-spectrum clocking.
91 * and pre-emphasis to requested values. Only lanes specified
/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_dpia.c44 link->ctx->logger
66 DPIA_TS_UFP_DONE = 0xff /* Done training DPTX-to-DPIA hop. */
95 * @param[out] lt_settings Link settings and drive settings (voltage swing and pre-emphasis).
106 DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n", in dpia_configure_link()
108 link->link_id.enum_id - ENUM_ID_1, in dpia_configure_link()
109 lt_settings->lttpr_mode); in dpia_configure_link()
116 dp_get_lttpr_mode_override(link, &lt_settings->lttpr_mode); in dpia_configure_link()
119 if (status != DC_OK && link->is_hpd_pending) in dpia_configure_link()
124 if (status != DC_OK && link->is_hpd_pending) in dpia_configure_link()
129 if (status != DC_OK && link->is_hpd_pending) in dpia_configure_link()
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/linux/drivers/gpu/drm/sti/
H A Dsti_hdmi_tx3g4c28phy.c1 // SPDX-License-Identifier: GPL-2.0
70 * sti_hdmi_tx3g4c28phy_start - Start hdmi phy macro cell tx3g4c28
78 u32 ckpxpll = hdmi->mode.clock * 1000; in sti_hdmi_tx3g4c28phy_start()
116 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_start()
121 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_start()
122 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_start()
142 * To configure the source termination and pre-emphasis appropriately in sti_hdmi_tx3g4c28phy_start()
168 * Default, power up the serializer with no pre-emphasis or in sti_hdmi_tx3g4c28phy_start()
182 * sti_hdmi_tx3g4c28phy_stop - Stop hdmi phy macro cell tx3g4c28
192 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_stop()
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/linux/include/sound/
H A Dak4117.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
27 #define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */
28 #define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */
29 #define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */
30 #define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */
31 #define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */
32 #define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */
33 #define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */
34 #define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */
35 #define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */
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H A Dak4113.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 /* Q-subcode address + control */
52 /* Q-subcode track */
54 /* Q-subcode index */
56 /* Q-subcode minute */
58 /* Q-subcode second */
60 /* Q-subcode frame */
62 /* Q-subcode zero */
64 /* Q-subcode absolute minute */
66 /* Q-subcode absolute second */
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/linux/arch/arm64/boot/dts/qcom/
H A Dsm8450-qrd.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
20 compatible = "qcom,sm8450-qrd", "qcom,sm8450";
21 chassis-type = "handset";
28 stdout-path = "serial0:115200n8";
31 vph_pwr: vph-pwr-regulator {
32 compatible = "regulator-fixed";
33 regulator-name = "vph_pwr";
34 regulator-min-microvolt = <3700000>;
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H A Dqcm6490-shift-otter.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
12 #include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
13 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
16 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
23 /delete-node/ &rmtfs_mem;
28 chassis-type = "handset";
36 #address-cells = <2>;
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H A Dqcm6490-fairphone-fp5.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
12 #include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
13 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
16 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
23 /delete-node/ &rmtfs_mem;
28 chassis-type = "handset";
36 #address-cells = <2>;
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/linux/drivers/media/radio/wl128x/
H A Dfmdrv_common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
129 #define fm_cb(skb) ((struct fm_skb_cb *)(skb->cb))
131 /* FM Channel-8 command message format */
133 __u8 hdr; /* Logical Channel-8 */
142 /* FM Channel-8 event messgage format */
144 __u8 header; /* Logical Channel-8 */
223 #define FM_RX_RSSI_THRESHOLD_MIN -128
231 /* FM RX De-emphasis filter modes */
347 /* FM TX Pre-emphasis filter values */
357 /* Functions exported by FM common sub-module */
/linux/drivers/gpu/drm/tegra/
H A Ddp.h1 /* SPDX-License-Identifier: MIT */
3 * Copyright (C) 2013-2019 NVIDIA Corporation.
18 * struct drm_dp_link_caps - DP link capabilities
61 * struct drm_dp_link_ops - DP link operations
80 * struct drm_dp_link_train_set - link training settings
81 * @voltage_swing: per-lane voltage swing
82 * @pre_emphasis: per-lane pre-emphasis
83 * @post_cursor: per-lane post-cursor
92 * struct drm_dp_link_train - link training state information
110 * struct drm_dp_link - DP link capabilities and configuration
/linux/drivers/gpu/drm/i915/display/
H A Dintel_fdi_regs.h1 /* SPDX-License-Identifier: MIT */
48 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
50 /* SNB A-stepping */
55 /* SNB B-stepping */
63 #define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
80 /* FDI_RX, FDI_X is hard-wired to Transcoder_X */
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-snps-femto-v2.c1 // SPDX-License-Identifier: GPL-2.0
82 "vdda-pll", "vdda33", "vdda18",
110 * struct qcom_snps_hsphy - snps hs phy attributes
143 struct device *dev = hsphy->dev; in qcom_snps_hsphy_clk_init()
145 hsphy->num_clks = 2; in qcom_snps_hsphy_clk_init()
146 hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL); in qcom_snps_hsphy_clk_init()
147 if (!hsphy->clks) in qcom_snps_hsphy_clk_init()
148 return -ENOMEM; in qcom_snps_hsphy_clk_init()
154 hsphy->clks[0].id = "cfg_ahb"; in qcom_snps_hsphy_clk_init()
155 hsphy->clks[0].clk = devm_clk_get_optional(dev, "cfg_ahb"); in qcom_snps_hsphy_clk_init()
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/linux/drivers/phy/lantiq/
H A Dphy-lantiq-rcu-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
21 /* Transmitter HS Pre-Emphasis Enable */
69 .compatible = "lantiq,ase-usb2-phy",
73 .compatible = "lantiq,danube-usb2-phy",
77 .compatible = "lantiq,xrx100-usb2-phy",
81 .compatible = "lantiq,xrx200-usb2-phy",
85 .compatible = "lantiq,xrx300-usb2-phy",
96 if (priv->reg_bits->have_ana_cfg) { in ltq_rcu_usb2_phy_init()
97 regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset, in ltq_rcu_usb2_phy_init()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_dp.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
34 #include "atom-bits.h"
63 struct drm_device *dev = chan->dev; in amdgpu_atombios_dp_process_aux_ch()
73 mutex_lock(&chan->mutex); in amdgpu_atombios_dp_process_aux_ch()
75 base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1); in amdgpu_atombios_dp_process_aux_ch()
82 args.v2.ucChannelID = chan->rec.i2c_id; in amdgpu_atombios_dp_process_aux_ch()
84 args.v2.ucHPD_ID = chan->rec.hpd; in amdgpu_atombios_dp_process_aux_ch()
86 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_dp_process_aux_ch()
92 r = -ETIMEDOUT; in amdgpu_atombios_dp_process_aux_ch()
99 r = -EIO; in amdgpu_atombios_dp_process_aux_ch()
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/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c1 // SPDX-License-Identifier: GPL-2.0
7 * Authors: Quentin Schulz <quentin.schulz@free-electrons.com>
14 * - Implement optimized mailbox communication using mailbox interrupts
15 * - Add support for power management
16 * - Add support for features like audio, MST and fast link training
17 * - Implement request_fw_cancel to handle HW_STATE
18 * - Fix asynchronous loading of firmware implementation
19 * - Add DRM helper function for cdns_mhdp_lower_link_rate
29 #include <linux/media-bus-format.h>
33 #include <linux/phy/phy-dp.h>
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/linux/drivers/gpu/drm/radeon/
H A Datombios_dp.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
32 #include "atom-bits.h"
90 struct drm_device *dev = chan->dev; in radeon_process_aux_ch()
91 struct radeon_device *rdev = dev->dev_private; in radeon_process_aux_ch()
100 mutex_lock(&chan->mutex); in radeon_process_aux_ch()
101 mutex_lock(&rdev->mode_info.atom_context->scratch_mutex); in radeon_process_aux_ch()
103 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); in radeon_process_aux_ch()
110 args.v1.ucChannelID = chan->rec.i2c_id; in radeon_process_aux_ch()
113 args.v2.ucHPD_ID = chan->rec.hpd; in radeon_process_aux_ch()
115 …atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof… in radeon_process_aux_ch()
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