Lines Matching +full:pre +full:- +full:emphasis
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
34 #include "atom-bits.h"
63 struct drm_device *dev = chan->dev; in amdgpu_atombios_dp_process_aux_ch()
73 mutex_lock(&chan->mutex); in amdgpu_atombios_dp_process_aux_ch()
75 base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1); in amdgpu_atombios_dp_process_aux_ch()
82 args.v2.ucChannelID = chan->rec.i2c_id; in amdgpu_atombios_dp_process_aux_ch()
84 args.v2.ucHPD_ID = chan->rec.hpd; in amdgpu_atombios_dp_process_aux_ch()
86 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_dp_process_aux_ch()
92 r = -ETIMEDOUT; in amdgpu_atombios_dp_process_aux_ch()
99 r = -EIO; in amdgpu_atombios_dp_process_aux_ch()
106 r = -EIO; in amdgpu_atombios_dp_process_aux_ch()
119 mutex_unlock(&chan->mutex); in amdgpu_atombios_dp_process_aux_ch()
137 if (WARN_ON(msg->size > 16)) in amdgpu_atombios_dp_aux_transfer()
138 return -E2BIG; in amdgpu_atombios_dp_aux_transfer()
140 tx_buf[0] = msg->address & 0xff; in amdgpu_atombios_dp_aux_transfer()
141 tx_buf[1] = msg->address >> 8; in amdgpu_atombios_dp_aux_transfer()
142 tx_buf[2] = (msg->request << 4) | in amdgpu_atombios_dp_aux_transfer()
143 ((msg->address >> 16) & 0xf); in amdgpu_atombios_dp_aux_transfer()
144 tx_buf[3] = msg->size ? (msg->size - 1) : 0; in amdgpu_atombios_dp_aux_transfer()
146 switch (msg->request & ~DP_AUX_I2C_MOT) { in amdgpu_atombios_dp_aux_transfer()
152 tx_size = HEADER_SIZE + msg->size; in amdgpu_atombios_dp_aux_transfer()
153 if (msg->size == 0) in amdgpu_atombios_dp_aux_transfer()
157 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); in amdgpu_atombios_dp_aux_transfer()
162 ret = msg->size; in amdgpu_atombios_dp_aux_transfer()
170 if (msg->size == 0) in amdgpu_atombios_dp_aux_transfer()
175 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); in amdgpu_atombios_dp_aux_transfer()
178 ret = -EINVAL; in amdgpu_atombios_dp_aux_transfer()
183 msg->reply = ack >> 4; in amdgpu_atombios_dp_aux_transfer()
190 amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd; in amdgpu_atombios_dp_aux_init()
191 amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer; in amdgpu_atombios_dp_aux_init()
192 amdgpu_connector->ddc_bus->aux.drm_dev = amdgpu_connector->base.dev; in amdgpu_atombios_dp_aux_init()
194 drm_dp_aux_init(&amdgpu_connector->ddc_bus->aux); in amdgpu_atombios_dp_aux_init()
195 amdgpu_connector->ddc_bus->has_aux = true; in amdgpu_atombios_dp_aux_init()
287 return -EINVAL; in amdgpu_atombios_dp_get_dp_link_config()
304 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args)); in amdgpu_atombios_dp_encoder_service()
310 struct drm_device *dev = amdgpu_connector->base.dev; in amdgpu_atombios_dp_get_sinktype()
314 amdgpu_connector->ddc_bus->rec.i2c_id, 0); in amdgpu_atombios_dp_get_sinktype()
319 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv; in amdgpu_atombios_dp_probe_oui()
322 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in amdgpu_atombios_dp_probe_oui()
325 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) in amdgpu_atombios_dp_probe_oui()
329 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) in amdgpu_atombios_dp_probe_oui()
336 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv; in amdgpu_atombios_dp_ds_ports()
339 if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) { in amdgpu_atombios_dp_ds_ports()
340 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, in amdgpu_atombios_dp_ds_ports()
342 dig_connector->downstream_ports, in amdgpu_atombios_dp_ds_ports()
345 memset(dig_connector->downstream_ports, 0, in amdgpu_atombios_dp_ds_ports()
352 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv; in amdgpu_atombios_dp_get_dpcd()
356 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV, in amdgpu_atombios_dp_get_dpcd()
359 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in amdgpu_atombios_dp_get_dpcd()
361 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in amdgpu_atombios_dp_get_dpcd()
362 dig_connector->dpcd); in amdgpu_atombios_dp_get_dpcd()
369 dig_connector->dpcd[0] = 0; in amdgpu_atombios_dp_get_dpcd()
370 return -EINVAL; in amdgpu_atombios_dp_get_dpcd()
381 if (!amdgpu_connector->con_priv) in amdgpu_atombios_dp_get_panel_mode()
386 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, in amdgpu_atombios_dp_get_panel_mode()
396 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { in amdgpu_atombios_dp_get_panel_mode()
398 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, in amdgpu_atombios_dp_get_panel_mode()
415 if (!amdgpu_connector->con_priv) in amdgpu_atombios_dp_set_link_config()
417 dig_connector = amdgpu_connector->con_priv; in amdgpu_atombios_dp_set_link_config()
419 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || in amdgpu_atombios_dp_set_link_config()
420 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { in amdgpu_atombios_dp_set_link_config()
421 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, in amdgpu_atombios_dp_set_link_config()
422 mode->clock, in amdgpu_atombios_dp_set_link_config()
423 &dig_connector->dp_lane_count, in amdgpu_atombios_dp_set_link_config()
424 &dig_connector->dp_clock); in amdgpu_atombios_dp_set_link_config()
426 dig_connector->dp_clock = 0; in amdgpu_atombios_dp_set_link_config()
427 dig_connector->dp_lane_count = 0; in amdgpu_atombios_dp_set_link_config()
440 if (!amdgpu_connector->con_priv) in amdgpu_atombios_dp_mode_valid_helper()
442 dig_connector = amdgpu_connector->con_priv; in amdgpu_atombios_dp_mode_valid_helper()
444 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, in amdgpu_atombios_dp_mode_valid_helper()
445 mode->clock, &dp_lanes, &dp_clock); in amdgpu_atombios_dp_mode_valid_helper()
459 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; in amdgpu_atombios_dp_needs_link_train()
461 if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status) in amdgpu_atombios_dp_needs_link_train()
464 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) in amdgpu_atombios_dp_needs_link_train()
475 if (!amdgpu_connector->con_priv) in amdgpu_atombios_dp_set_rx_power_state()
478 dig_connector = amdgpu_connector->con_priv; in amdgpu_atombios_dp_set_rx_power_state()
481 if (dig_connector->dpcd[0] >= 0x11) { in amdgpu_atombios_dp_set_rx_power_state()
482 drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux, in amdgpu_atombios_dp_set_rx_power_state()
506 amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder, in amdgpu_atombios_dp_update_vs_emph()
508 0, dp_info->train_set[0]); /* sets all lanes at once */ in amdgpu_atombios_dp_update_vs_emph()
511 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, in amdgpu_atombios_dp_update_vs_emph()
512 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph()
532 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0); in amdgpu_atombios_dp_set_tp()
535 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); in amdgpu_atombios_dp_set_tp()
541 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder); in amdgpu_atombios_dp_link_train_init()
542 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in amdgpu_atombios_dp_link_train_init()
546 amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); in amdgpu_atombios_dp_link_train_init()
549 if (dp_info->dpcd[3] & 0x1) in amdgpu_atombios_dp_link_train_init()
550 drm_dp_dpcd_writeb(dp_info->aux, in amdgpu_atombios_dp_link_train_init()
553 drm_dp_dpcd_writeb(dp_info->aux, in amdgpu_atombios_dp_link_train_init()
556 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) in amdgpu_atombios_dp_link_train_init()
557 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); in amdgpu_atombios_dp_link_train_init()
560 tmp = dp_info->dp_lane_count; in amdgpu_atombios_dp_link_train_init()
561 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) in amdgpu_atombios_dp_link_train_init()
563 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); in amdgpu_atombios_dp_link_train_init()
566 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); in amdgpu_atombios_dp_link_train_init()
567 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); in amdgpu_atombios_dp_link_train_init()
570 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, in amdgpu_atombios_dp_link_train_init()
574 drm_dp_dpcd_writeb(dp_info->aux, in amdgpu_atombios_dp_link_train_init()
587 drm_dp_dpcd_writeb(dp_info->aux, in amdgpu_atombios_dp_link_train_finish()
592 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, in amdgpu_atombios_dp_link_train_finish()
606 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr()
613 dp_info->tries = 0; in amdgpu_atombios_dp_link_train_cr()
616 drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd); in amdgpu_atombios_dp_link_train_cr()
618 if (drm_dp_dpcd_read_link_status(dp_info->aux, in amdgpu_atombios_dp_link_train_cr()
619 dp_info->link_status) <= 0) { in amdgpu_atombios_dp_link_train_cr()
624 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { in amdgpu_atombios_dp_link_train_cr()
629 for (i = 0; i < dp_info->dp_lane_count; i++) { in amdgpu_atombios_dp_link_train_cr()
630 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in amdgpu_atombios_dp_link_train_cr()
633 if (i == dp_info->dp_lane_count) { in amdgpu_atombios_dp_link_train_cr()
638 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in amdgpu_atombios_dp_link_train_cr()
639 ++dp_info->tries; in amdgpu_atombios_dp_link_train_cr()
640 if (dp_info->tries == 5) { in amdgpu_atombios_dp_link_train_cr()
645 dp_info->tries = 0; in amdgpu_atombios_dp_link_train_cr()
647 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in amdgpu_atombios_dp_link_train_cr()
650 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, in amdgpu_atombios_dp_link_train_cr()
651 dp_info->train_set); in amdgpu_atombios_dp_link_train_cr()
657 return -1; in amdgpu_atombios_dp_link_train_cr()
659 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", in amdgpu_atombios_dp_link_train_cr()
660 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in amdgpu_atombios_dp_link_train_cr()
661 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in amdgpu_atombios_dp_link_train_cr()
672 if (dp_info->tp3_supported) in amdgpu_atombios_dp_link_train_ce()
678 dp_info->tries = 0; in amdgpu_atombios_dp_link_train_ce()
681 drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); in amdgpu_atombios_dp_link_train_ce()
683 if (drm_dp_dpcd_read_link_status(dp_info->aux, in amdgpu_atombios_dp_link_train_ce()
684 dp_info->link_status) <= 0) { in amdgpu_atombios_dp_link_train_ce()
689 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { in amdgpu_atombios_dp_link_train_ce()
695 if (dp_info->tries > 5) { in amdgpu_atombios_dp_link_train_ce()
701 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, in amdgpu_atombios_dp_link_train_ce()
702 dp_info->train_set); in amdgpu_atombios_dp_link_train_ce()
705 dp_info->tries++; in amdgpu_atombios_dp_link_train_ce()
710 return -1; in amdgpu_atombios_dp_link_train_ce()
712 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", in amdgpu_atombios_dp_link_train_ce()
713 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, in amdgpu_atombios_dp_link_train_ce()
714 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) in amdgpu_atombios_dp_link_train_ce()
723 struct drm_device *dev = encoder->dev; in amdgpu_atombios_dp_link_train()
731 if (!amdgpu_encoder->enc_priv) in amdgpu_atombios_dp_link_train()
735 if (!amdgpu_connector->con_priv) in amdgpu_atombios_dp_link_train()
737 dig_connector = amdgpu_connector->con_priv; in amdgpu_atombios_dp_link_train()
739 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && in amdgpu_atombios_dp_link_train()
740 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) in amdgpu_atombios_dp_link_train()
743 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) in amdgpu_atombios_dp_link_train()
753 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in amdgpu_atombios_dp_link_train()
757 dp_info.dp_lane_count = dig_connector->dp_lane_count; in amdgpu_atombios_dp_link_train()
758 dp_info.dp_clock = dig_connector->dp_clock; in amdgpu_atombios_dp_link_train()
759 dp_info.aux = &amdgpu_connector->ddc_bus->aux; in amdgpu_atombios_dp_link_train()