| /linux/drivers/gpu/drm/virtio/ |
| H A D | virtgpu_plane.c | 74 drm_plane_state *virtio_gpu_plane_duplicate_state(struct drm_plane *plane) in virtio_gpu_plane_duplicate_state() argument
78 if (WARN_ON(!plane->state)) in virtio_gpu_plane_duplicate_state()
85 __drm_atomic_helper_plane_duplicate_state(plane, &new->base); in virtio_gpu_plane_duplicate_state()
98 static int virtio_gpu_plane_atomic_check(struct drm_plane *plane, in virtio_gpu_plane_atomic_check() argument
102 plane); in virtio_gpu_plane_atomic_check()
104 plane); in virtio_gpu_plane_atomic_check()
105 bool is_cursor = plane->type == DRM_PLANE_TYPE_CURSOR; in virtio_gpu_plane_atomic_check()
113 * Ignore damage clips if the framebuffer attached to the plane's state in virtio_gpu_plane_atomic_check()
114 * has changed since the last plane update (page-flip). In this case, a in virtio_gpu_plane_atomic_check()
115 * full plane update should happen because uploads are done per-buffer. in virtio_gpu_plane_atomic_check()
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| /linux/drivers/gpu/drm/nouveau/dispnv04/ |
| H A D | overlay.c | 113 nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, in nv10_update_plane() argument
120 struct nouveau_drm *drm = nouveau_drm(plane->dev); in nv10_update_plane()
123 container_of(plane, struct nouveau_plane, base); in nv10_update_plane()
192 nv10_disable_plane(struct drm_plane *plane, in nv10_disable_plane() argument
195 struct nvif_object *dev = &nouveau_drm(plane->dev)->client.device.object; in nv10_disable_plane()
197 container_of(plane, struct nouveau_plane, base); in nv10_disable_plane()
209 nv_destroy_plane(struct drm_plane *plane) in nv_destroy_plane() argument
211 drm_plane_force_disable(plane); in nv_destroy_plane()
212 drm_plane_cleanup(plane); in nv_destroy_plane()
213 kfree(plane); in nv_destroy_plane()
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| /linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_plane.c | 30 static void mtk_plane_reset(struct drm_plane *plane) in mtk_plane_reset() argument
34 if (plane->state) { in mtk_plane_reset()
35 __drm_atomic_helper_plane_destroy_state(plane->state); in mtk_plane_reset()
37 state = to_mtk_plane_state(plane->state); in mtk_plane_reset()
45 __drm_atomic_helper_plane_reset(plane, &state->base); in mtk_plane_reset()
47 state->base.plane = plane; in mtk_plane_reset()
52 static struct drm_plane_state *mtk_plane_duplicate_state(struct drm_plane *plane) in mtk_plane_duplicate_state() argument
54 struct mtk_plane_state *old_state = to_mtk_plane_state(plane->state); in mtk_plane_duplicate_state()
61 __drm_atomic_helper_plane_duplicate_state(plane, &state->base); in mtk_plane_duplicate_state()
63 WARN_ON(state->base.plane != plane); in mtk_plane_duplicate_state()
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| /linux/drivers/gpu/drm/omapdrm/ |
| H A D | omap_plane.c | 18 * plane funcs
45 static int omap_plane_prepare_fb(struct drm_plane *plane, in omap_plane_prepare_fb() argument
51 drm_gem_plane_helper_prepare_fb(plane, new_state); in omap_plane_prepare_fb()
56 static void omap_plane_cleanup_fb(struct drm_plane *plane, in omap_plane_cleanup_fb() argument
63 static void omap_plane_atomic_update(struct drm_plane *plane, in omap_plane_atomic_update() argument
66 struct omap_drm_private *priv = plane->dev->dev_private; in omap_plane_atomic_update()
68 plane); in omap_plane_atomic_update()
70 plane); in omap_plane_atomic_update()
90 DBG("[PLANE:%d:%s] no overlay attached", plane->base.id, plane->name); in omap_plane_atomic_update()
95 DBG("%s, crtc=%p fb=%p", plane->name, new_state->crtc, in omap_plane_atomic_update()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | skl_universal_plane_regs.h | 11 #define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
12 _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b)))
13 #define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
14 (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4)
15 #define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
16 _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
17 #define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ argument
18 _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
20 #define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_… argument
21 _PICK_EVEN_2RANGES((plane), PLANE_5, \
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| H A D | i9xx_plane_regs.h | 12 #define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) argument
15 #define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) argument
41 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) /* pre-g4x plane B */
46 #define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) /* pre-g4x plane B/C */
49 #define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) argument
52 #define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) argument
55 #define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) argument
58 #define DSPPOS(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) argument
65 #define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) argument
72 #define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) argument
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| H A D | intel_fbc.c | 87 struct intel_plane *plane; member
135 /* plane stride in pixels */
153 /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
207 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_cfb_stride()
217 * additional lines (up to the actual plane height) will
238 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_cfb_size()
246 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_override_cfb_stride()
309 FBC_CTL_PLANE(fbc_state->plane->i9xx_plane); in i965_fbc_ctl2()
374 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; in i8xx_fbc_nuke()
412 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; in i965_fbc_nuke()
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| /linux/drivers/gpu/drm/atmel-hlcdc/ |
| H A D | atmel_hlcdc_plane.c | 23 * struct atmel_hlcdc_plane_state - Atmel HLCDC Plane state structure.
25 * @base: DRM plane state
26 * @crtc_x: x position of the plane relative to the CRTC
27 * @crtc_y: y position of the plane relative to the CRTC
28 * @crtc_w: visible width of the plane
29 * @crtc_h: visible height of the plane
274 atmel_hlcdc_plane_scaler_set_phicoeff(struct atmel_hlcdc_plane *plane, in atmel_hlcdc_plane_scaler_set_phicoeff() argument
281 atmel_hlcdc_layer_write_cfg(&plane->layer, cfg_offs + i, in atmel_hlcdc_plane_scaler_set_phicoeff()
286 void atmel_hlcdc_plane_setup_scaler(struct atmel_hlcdc_plane *plane, in atmel_hlcdc_plane_setup_scaler() argument
289 const struct atmel_hlcdc_layer_desc *desc = plane->layer.desc; in atmel_hlcdc_plane_setup_scaler()
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| /linux/drivers/gpu/drm/arm/display/komeda/ |
| H A D | komeda_plane.c | 20 struct komeda_plane *kplane = to_kplane(st->plane); in komeda_plane_init_data_flow()
32 st->plane->name, st->normalized_zpos, in komeda_plane_init_data_flow()
64 * @plane: DRM plane
65 * @state: the plane state object
71 komeda_plane_atomic_check(struct drm_plane *plane, in komeda_plane_atomic_check() argument
75 plane); in komeda_plane_atomic_check()
76 struct komeda_plane *kplane = to_kplane(plane); in komeda_plane_atomic_check()
90 DRM_DEBUG_ATOMIC("Cannot update plane on a disabled CRTC.\n"); in komeda_plane_atomic_check()
114 /* plane doesn't represent a real HW, so there is no HW update for plane.
118 komeda_plane_atomic_update(struct drm_plane *plane, in komeda_plane_atomic_update() argument
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| /linux/drivers/gpu/drm/omapdrm/dss/ |
| H A D | dispc.h | 342 static inline u16 DISPC_OVL_BASE(enum omap_plane_id plane) in DISPC_OVL_BASE() argument
344 switch (plane) { in DISPC_OVL_BASE()
362 static inline u16 DISPC_BA0_OFFSET(enum omap_plane_id plane) in DISPC_BA0_OFFSET() argument
364 switch (plane) { in DISPC_BA0_OFFSET()
378 static inline u16 DISPC_BA1_OFFSET(enum omap_plane_id plane) in DISPC_BA1_OFFSET() argument
380 switch (plane) { in DISPC_BA1_OFFSET()
394 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane_id plane) in DISPC_BA0_UV_OFFSET() argument
396 switch (plane) { in DISPC_BA0_UV_OFFSET()
414 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane_id plane) in DISPC_BA1_UV_OFFSET() argument
416 switch (plane) { in DISPC_BA1_UV_OFFSET()
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| /linux/drivers/video/fbdev/omap2/omapfb/dss/ |
| H A D | dispc.h | 339 static inline u16 DISPC_OVL_BASE(enum omap_plane plane) in DISPC_OVL_BASE() argument
341 switch (plane) { in DISPC_OVL_BASE()
359 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane) in DISPC_BA0_OFFSET() argument
361 switch (plane) { in DISPC_BA0_OFFSET()
375 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane) in DISPC_BA1_OFFSET() argument
377 switch (plane) { in DISPC_BA1_OFFSET()
391 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane) in DISPC_BA0_UV_OFFSET() argument
393 switch (plane) { in DISPC_BA0_UV_OFFSET()
411 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane) in DISPC_BA1_UV_OFFSET() argument
413 switch (plane) { in DISPC_BA1_UV_OFFSET()
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| /linux/drivers/gpu/drm/tegra/ |
| H A D | plane.c | 17 #include "plane.h"
19 static void tegra_plane_destroy(struct drm_plane *plane) in tegra_plane_destroy() argument
21 struct tegra_plane *p = to_tegra_plane(plane); in tegra_plane_destroy()
23 drm_plane_cleanup(plane); in tegra_plane_destroy()
27 static void tegra_plane_reset(struct drm_plane *plane) in tegra_plane_reset() argument
29 struct tegra_plane *p = to_tegra_plane(plane); in tegra_plane_reset()
33 if (plane->state) in tegra_plane_reset()
34 __drm_atomic_helper_plane_destroy_state(plane->state); in tegra_plane_reset()
36 kfree(plane->state); in tegra_plane_reset()
37 plane->state = NULL; in tegra_plane_reset()
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| /linux/drivers/gpu/drm/sun4i/ |
| H A D | sun4i_layer.c | 19 static void sun4i_backend_layer_reset(struct drm_plane *plane) in sun4i_backend_layer_reset() argument
23 if (plane->state) { in sun4i_backend_layer_reset()
24 state = state_to_sun4i_layer_state(plane->state); in sun4i_backend_layer_reset()
29 plane->state = NULL; in sun4i_backend_layer_reset()
34 __drm_atomic_helper_plane_reset(plane, &state->state); in sun4i_backend_layer_reset()
38 sun4i_backend_layer_duplicate_state(struct drm_plane *plane) in sun4i_backend_layer_duplicate_state() argument
40 struct sun4i_layer_state *orig = state_to_sun4i_layer_state(plane->state); in sun4i_backend_layer_duplicate_state()
47 __drm_atomic_helper_plane_duplicate_state(plane, ©->state); in sun4i_backend_layer_duplicate_state()
53 static void sun4i_backend_layer_destroy_state(struct drm_plane *plane, in sun4i_backend_layer_destroy_state() argument
63 static void sun4i_backend_layer_atomic_disable(struct drm_plane *plane, in sun4i_backend_layer_atomic_disable() argument
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| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_plane.c | 31 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\
34 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\
74 * struct dpu_plane - local dpu plane structure
78 * @revalidate: force revalidation of all the plane properties
99 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane) in _dpu_plane_get_kms() argument
101 struct msm_drm_private *priv = plane->dev->dev_private; in _dpu_plane_get_kms()
107 * _dpu_plane_calc_bw - calculate bandwidth required for a plane
112 * Result: Updates calculated bandwidth in the plane state.
159 * _dpu_plane_calc_clk - calculate clock required for a plane
162 * Result: Updates calculated clock in the plane state.
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| /linux/Documentation/gpu/ |
| H A D | afbc.rst | 87 Within each plane, the component ordering also follows the fourcc
94 * Plane 0:
102 * Plane 0:
106 * Plane 1:
127 - Plane 0: 4 components
135 - Plane 0: 4 components
143 - Plane 0: 3 components
150 - Plane 0: 3 components
157 - Plane 0: 4 components
164 - 8-bit per component YCbCr 444, single plane
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| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | mpo-overview.rst | 17 * Plane independent page flips - No need to be tied to global compositor
31 * ``DRM_PLANE_TYPE_PRIMARY``: Primary planes represent a "main" plane for a
34 * ``DRM_PLANE_TYPE_CURSOR``: Cursor planes represent a "cursor" plane for a
45 * 1 Overlay plane (shared among CRTCs).
53 configuration for optimal single display output (e.g., 2 pipes per plane).
56 display - will see 4 pipes in use, 2 per plane.
58 At least 1 pipe must be used per plane (primary and overlay), so for this
65 Plane Restrictions
78 Not every property is available on every plane:
94 plane as it is being treated as part of the plane. Another consequence of that
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| /linux/drivers/gpu/drm/renesas/rcar-du/ |
| H A D | rcar_du_vsp.c | 219 static void rcar_du_vsp_plane_setup(struct rcar_du_vsp_plane *plane) in rcar_du_vsp_plane_setup() argument
222 to_rcar_vsp_plane_state(plane->plane.state); in rcar_du_vsp_plane_setup()
224 struct drm_framebuffer *fb = plane->plane.state->fb; in rcar_du_vsp_plane_setup()
254 vsp1_du_atomic_update(plane->vsp->vsp, crtc->vsp_pipe, in rcar_du_vsp_plane_setup()
255 plane->index, &cfg); in rcar_du_vsp_plane_setup()
320 static int rcar_du_vsp_plane_prepare_fb(struct drm_plane *plane, in rcar_du_vsp_plane_prepare_fb() argument
324 struct rcar_du_vsp *vsp = to_rcar_vsp_plane(plane)->vsp; in rcar_du_vsp_plane_prepare_fb()
329 * plane is not visible, as it will not be displayed. in rcar_du_vsp_plane_prepare_fb()
338 return drm_gem_plane_helper_prepare_fb(plane, state); in rcar_du_vsp_plane_prepare_fb()
354 static void rcar_du_vsp_plane_cleanup_fb(struct drm_plane *plane, in rcar_du_vsp_plane_cleanup_fb() argument
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_plane.c | 46 * plane capabilities, or initialize this array to all formats, so internal drm
393 /* TODO: This seems wrong because there is no DCC plane on GFX12. */ in amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers()
779 static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane, in amdgpu_dm_plane_get_plane_formats() argument
787 * DC plane caps. This will require adding more formats to the in amdgpu_dm_plane_get_plane_formats()
791 if (plane->type == DRM_PLANE_TYPE_PRIMARY || in amdgpu_dm_plane_get_plane_formats()
792 …(plane_cap && plane_cap->type == DC_PLANE_TYPE_DCN_UNIVERSAL && plane->type != DRM_PLANE_TYPE_CURS… in amdgpu_dm_plane_get_plane_formats()
811 switch (plane->type) { in amdgpu_dm_plane_get_plane_formats()
924 static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, in amdgpu_dm_plane_helper_prepare_fb() argument
961 if (plane->type != DRM_PLANE_TYPE_CURSOR) in amdgpu_dm_plane_helper_prepare_fb()
980 r = drm_gem_plane_helper_prepare_fb(plane, new_state); in amdgpu_dm_plane_helper_prepare_fb()
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| /linux/drivers/gpu/drm/kmb/ |
| H A D | kmb_plane.c | 67 static unsigned int check_pixel_format(struct drm_plane *plane, u32 format) in check_pixel_format() argument
70 struct kmb_plane *kmb_plane = to_kmb_plane(plane); in check_pixel_format()
75 kmb = to_kmb(plane->dev); in check_pixel_format()
78 * plane configuration is not supported. in check_pixel_format()
81 drm_dbg(&kmb->drm, "Cannot change format after initial plane configuration"); in check_pixel_format()
84 for (i = 0; i < plane->format_count; i++) { in check_pixel_format()
85 if (plane->format_types[i] == format) in check_pixel_format()
91 static int kmb_plane_atomic_check(struct drm_plane *plane, in kmb_plane_atomic_check() argument
95 plane); in kmb_plane_atomic_check()
97 struct kmb_plane *kmb_plane = to_kmb_plane(plane); in kmb_plane_atomic_check()
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| /linux/drivers/gpu/drm/sti/ |
| H A D | sti_plane.c | 20 const char *sti_plane_to_str(struct sti_plane *plane) in sti_plane_to_str() argument
22 switch (plane->desc) { in sti_plane_to_str()
36 return "<UNKNOWN PLANE>"; in sti_plane_to_str()
42 void sti_plane_update_fps(struct sti_plane *plane, in sti_plane_update_fps() argument
46 struct drm_plane_state *state = plane->drm_plane.state; in sti_plane_update_fps()
54 fps = &plane->fps_info; in sti_plane_update_fps()
75 snprintf(plane->fps_info.fps_str, FPS_LENGTH, in sti_plane_update_fps()
77 plane->drm_plane.name, in sti_plane_update_fps()
82 sti_plane_to_str(plane)); in sti_plane_update_fps()
90 snprintf(plane->fps_info.fips_str, in sti_plane_update_fps()
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| H A D | sti_crtc.c | 146 /* perform plane actions */ in sti_crtc_atomic_flush()
148 struct sti_plane *plane = to_sti_plane(p); in sti_crtc_atomic_flush() local
150 switch (plane->status) { in sti_crtc_atomic_flush()
157 DRM_DEBUG_DRIVER("update plane %s\n", in sti_crtc_atomic_flush()
158 sti_plane_to_str(plane)); in sti_crtc_atomic_flush()
160 if (sti_mixer_set_plane_depth(mixer, plane)) { in sti_crtc_atomic_flush()
161 DRM_ERROR("Cannot set plane %s depth\n", in sti_crtc_atomic_flush()
162 sti_plane_to_str(plane)); in sti_crtc_atomic_flush()
166 if (sti_mixer_set_plane_status(mixer, plane, true)) { in sti_crtc_atomic_flush()
167 DRM_ERROR("Cannot enable plane %s at mixer\n", in sti_crtc_atomic_flush()
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| /linux/drivers/gpu/drm/exynos/ |
| H A D | exynos_drm_plane.c | 112 /* set plane range to be displayed. */ in exynos_plane_mode_set()
119 "plane : offset_x/y(%d,%d), width/height(%d,%d)", in exynos_plane_mode_set()
124 static void exynos_drm_plane_reset(struct drm_plane *plane) in exynos_drm_plane_reset() argument
126 struct exynos_drm_plane *exynos_plane = to_exynos_plane(plane); in exynos_drm_plane_reset()
129 if (plane->state) { in exynos_drm_plane_reset()
130 exynos_state = to_exynos_plane_state(plane->state); in exynos_drm_plane_reset()
131 __drm_atomic_helper_plane_destroy_state(plane->state); in exynos_drm_plane_reset()
133 plane->state = NULL; in exynos_drm_plane_reset()
138 __drm_atomic_helper_plane_reset(plane, &exynos_state->base); in exynos_drm_plane_reset()
139 plane->state->zpos = exynos_plane->config->zpos; in exynos_drm_plane_reset()
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| /linux/drivers/media/common/videobuf2/ |
| H A D | videobuf2-core.c | 227 int plane; in __vb2_buf_mem_alloc() local
234 for (plane = 0; plane < vb->num_planes; ++plane) { in __vb2_buf_mem_alloc()
236 unsigned long size = PAGE_ALIGN(vb->planes[plane].length); in __vb2_buf_mem_alloc()
239 if (size < vb->planes[plane].length) in __vb2_buf_mem_alloc()
244 q->alloc_devs[plane] ? : q->dev, in __vb2_buf_mem_alloc()
252 /* Associate allocator private data with this plane */ in __vb2_buf_mem_alloc()
253 vb->planes[plane].mem_priv = mem_priv; in __vb2_buf_mem_alloc()
259 for (; plane > 0; --plane) { in __vb2_buf_mem_alloc()
260 call_void_memop(vb, put, vb->planes[plane - 1].mem_priv); in __vb2_buf_mem_alloc()
261 vb->planes[plane - 1].mem_priv = NULL; in __vb2_buf_mem_alloc()
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| /linux/include/drm/ |
| H A D | drm_gem_atomic_helper.h | 15 * Plane Helpers
18 int drm_gem_plane_helper_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state);
25 * DRM_SHADOW_PLANE_MAX_WIDTH - Maximum width of a plane's shadow buffer in pixels
34 * DRM_SHADOW_PLANE_MAX_HEIGHT - Maximum height of a plane's shadow buffer in scanlines
43 * struct drm_shadow_plane_state - plane state for planes with shadow buffers
46 * provides the regular plane state plus mappings of the shadow buffer
50 /** @base: plane state */
56 * Per-plane state for format conversion.
65 * @map: Mappings of the plane's framebuffer BOs in to kernel address space
67 * The memory mappings stored in map should be established in the plane's
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | display_mode_util.c | 404 …Immediate Flip Supported : %s\n", ((mode_lib->ms.cache_display_cfg.plane.HostVMEnable == fa… in dml_print_mode_support()
530 dml_print("DML: timing_cfg: plane=%d, HTotal = %d\n", i, timing->HTotal[i]); in dml_print_dml_display_cfg_timing()
531 dml_print("DML: timing_cfg: plane=%d, VTotal = %d\n", i, timing->VTotal[i]); in dml_print_dml_display_cfg_timing()
532 dml_print("DML: timing_cfg: plane=%d, HActive = %d\n", i, timing->HActive[i]); in dml_print_dml_display_cfg_timing()
533 dml_print("DML: timing_cfg: plane=%d, VActive = %d\n", i, timing->VActive[i]); in dml_print_dml_display_cfg_timing()
534 dml_print("DML: timing_cfg: plane=%d, VFrontPorch = %d\n", i, timing->VFrontPorch[i]); in dml_print_dml_display_cfg_timing()
535 dml_print("DML: timing_cfg: plane=%d, VBlankNom = %d\n", i, timing->VBlankNom[i]); in dml_print_dml_display_cfg_timing()
536 dml_print("DML: timing_cfg: plane=%d, RefreshRate = %d\n", i, timing->RefreshRate[i]); in dml_print_dml_display_cfg_timing()
537 dml_print("DML: timing_cfg: plane=%d, PixelClock = %f\n", i, timing->PixelClock[i]); in dml_print_dml_display_cfg_timing()
538 dml_print("DML: timing_cfg: plane=%d, Interlace = %d\n", i, timing->Interlace[i]); in dml_print_dml_display_cfg_timing()
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