Lines Matching full:plane
37 #include "plane.h"
62 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
67 return plane->offset + offset;
72 return plane->offset + offset;
77 return plane->offset + offset;
80 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
82 return plane->offset + offset;
85 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
88 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
91 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
94 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
168 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
183 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
184 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
186 state = to_tegra_plane_state(plane->base.state);
196 * plane.
263 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
264 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
265 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
282 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
283 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
284 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
288 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
289 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
290 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
295 static void tegra_plane_setup_blending(struct tegra_plane *plane,
303 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
308 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
311 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
315 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
318 struct tegra_dc *dc = plane->dc;
323 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
330 tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
333 struct tegra_dc *dc = plane->dc;
338 if (plane->index == 0 && dc->soc->has_win_a_without_filters)
341 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
347 static void tegra_dc_setup_window(struct tegra_plane *plane,
351 struct tegra_dc *dc = plane->dc;
366 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
367 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
370 tegra_plane_writel(plane, value, DC_WIN_POSITION);
373 tegra_plane_writel(plane, value, DC_WIN_SIZE);
387 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
400 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
405 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
406 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
408 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
409 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
411 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
414 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
417 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
420 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
422 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
425 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
426 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
446 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
467 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
474 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
475 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
476 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
477 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
478 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
479 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
480 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
481 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
494 if (tegra_plane_use_horizontal_filtering(plane, window)) {
499 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
500 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
501 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
502 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
503 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
504 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
505 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
506 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
507 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
508 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
509 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
510 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
511 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
512 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
513 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
514 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
519 if (tegra_plane_use_vertical_filtering(plane, window)) {
527 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
532 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
535 tegra_plane_setup_blending_legacy(plane);
537 tegra_plane_setup_blending(plane, window);
618 static int tegra_plane_atomic_check(struct drm_plane *plane,
622 plane);
629 struct tegra_plane *tegra = to_tegra_plane(plane);
636 /* no need for further checks if the plane is being disabled */
652 * be emulated by disabling alpha blending for the plane.
698 DRM_ERROR("unsupported UV-plane configuration\n");
710 static void tegra_plane_atomic_disable(struct drm_plane *plane,
714 plane);
715 struct tegra_plane *p = to_tegra_plane(plane);
727 static void tegra_plane_atomic_update(struct drm_plane *plane,
731 plane);
734 struct tegra_plane *p = to_tegra_plane(plane);
743 return tegra_plane_atomic_disable(plane, state);
770 * function, so it's safe to ignore the V-plane pitch here.
809 struct tegra_plane *plane;
815 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
816 if (!plane)
820 plane->offset = 0xa00;
821 plane->index = 0;
822 plane->dc = dc;
828 err = tegra_plane_interconnect_init(plane);
830 kfree(plane);
834 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
838 kfree(plane);
842 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
843 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
845 err = drm_plane_create_rotation_property(&plane->base,
855 return &plane->base;
866 static int tegra_cursor_atomic_check(struct drm_plane *plane,
870 plane);
872 struct tegra_plane *tegra = to_tegra_plane(plane);
878 /* no need for further checks if the plane is being disabled */
904 static void __tegra_cursor_atomic_update(struct drm_plane *plane,
909 struct tegra_drm *tegra = plane->dev->dev_private;
1002 static void tegra_cursor_atomic_update(struct drm_plane *plane,
1005 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1007 __tegra_cursor_atomic_update(plane, new_state);
1010 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
1014 plane);
1029 static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_atomic_state *state,
1032 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1044 if (plane->state->crtc != new_state->crtc ||
1045 plane->state->src_w != new_state->src_w ||
1046 plane->state->src_h != new_state->src_h ||
1047 plane->state->crtc_w != new_state->crtc_w ||
1048 plane->state->crtc_h != new_state->crtc_h ||
1049 plane->state->fb != new_state->fb ||
1050 plane->state->fb == NULL)
1061 if (new_state->visible != plane->state->visible)
1067 static void tegra_cursor_atomic_async_update(struct drm_plane *plane,
1070 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1073 plane->state->src_x = new_state->src_x;
1074 plane->state->src_y = new_state->src_y;
1075 plane->state->crtc_x = new_state->crtc_x;
1076 plane->state->crtc_y = new_state->crtc_y;
1079 struct tegra_plane *p = to_tegra_plane(plane);
1082 __tegra_cursor_atomic_update(plane, new_state);
1113 struct tegra_plane *plane;
1118 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1119 if (!plane)
1123 * This index is kind of fake. The cursor isn't a regular plane, but
1127 * need to special-casing the cursor plane.
1129 plane->index = 6;
1130 plane->dc = dc;
1136 err = tegra_plane_interconnect_init(plane);
1138 kfree(plane);
1146 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1151 kfree(plane);
1155 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
1156 drm_plane_create_zpos_immutable_property(&plane->base, 255);
1158 return &plane->base;
1260 struct tegra_plane *plane;
1266 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
1267 if (!plane)
1270 plane->offset = 0xa00 + 0x200 * index;
1271 plane->index = index;
1272 plane->dc = dc;
1277 err = tegra_plane_interconnect_init(plane);
1279 kfree(plane);
1288 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
1293 kfree(plane);
1297 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
1298 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
1300 err = drm_plane_create_rotation_property(&plane->base,
1310 return &plane->base;
1316 struct drm_plane *plane, *primary = NULL;
1332 plane = tegra_shared_plane_create(drm, dc,
1335 if (IS_ERR(plane))
1336 return plane;
1339 * Choose the first shared plane owned by this
1340 * head as the primary plane.
1343 primary = plane;
2011 struct drm_plane *plane;
2027 drm_atomic_crtc_for_each_plane(plane, crtc) {
2028 tegra = to_tegra_plane(plane);
2037 for_each_old_plane_in_state(old_crtc_state->state, plane,
2040 new_tegra_state = to_const_tegra_plane_state(plane->state);
2041 tegra = to_tegra_plane(plane);
2066 window.src.h = drm_rect_height(&plane->state->src) >> 16;
2067 window.dst.h = drm_rect_height(&plane->state->dst);
2337 if (state->plane->type != DRM_PLANE_TYPE_CURSOR)
2356 struct drm_plane *plane;
2364 * pressure if other plane overlaps with the cursor plane.
2369 drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) {
2372 tegra = to_tegra_plane(other_state->plane);
2378 * Ignore cursor plane overlaps because it's not practical to
2403 struct drm_plane *plane;
2417 * For overlapping planes pixel's data is fetched for each plane at
2422 * Here we get the overlapping state of each plane, which is a
2423 * bitmask of plane indices telling with what planes there is an
2424 * overlap. Note that bitmask[plane] includes BIT(plane) in order
2427 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
2429 tegra = to_tegra_plane(plane);
2443 * Then we calculate maximum bandwidth of each plane state.
2444 * The bandwidth includes the plane BW + BW of the "simultaneously"
2448 * For example, if plane A overlaps with planes B and C, but B and C
2453 * each plane, this information is needed by interconnect provider
2457 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) {
2461 * Note that plane's atomic check doesn't touch the
2462 * total_peak_memory_bandwidth of enabled plane, hence the
2467 tegra = to_tegra_plane(plane);
2483 * If plane's peak bandwidth changed (for example plane isn't
2484 * overlapped anymore) and plane isn't in the atomic state,
2485 * then add plane to the state in order to have the bandwidth
2492 new_plane_state = drm_atomic_get_plane_state(state, plane);
2630 * assign a primary plane to them, which in turn will cause KMS to