| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | pmu.yaml | 4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
25 - apple,firestorm-pmu
26 - apple,icestorm-pmu
28 - arm,arm1136-pmu
29 - arm,arm1176-pmu
[all …]
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| H A D | arm-dsu-pmu.txt | 1 * ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
5 form a multicore cluster. The PMU enables to gather various statistics on
6 the operations of the DSU. The PMU provides independent 32bit counters that
8 The PMU is accessed via CPU system registers and has no MMIO component.
10 ** DSU PMU required properties:
14 "arm,dsu-pmu"
23 dsu-pmu-0 {
24 compatible = "arm,dsu-pmu";
|
| /freebsd/sys/contrib/device-tree/Bindings/soc/samsung/ |
| H A D | exynos-pmu.yaml | 4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
7 title: Samsung Exynos SoC series Power Management Unit (PMU)
18 - google,gs101-pmu
19 - samsung,exynos3250-pmu
20 - samsung,exynos4210-pmu
21 - samsung,exynos4212-pmu
22 - samsung,exynos4412-pmu
23 - samsung,exynos5250-pmu
24 - samsung,exynos5260-pmu
25 - samsung,exynos5410-pmu
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/arm/samsung/ |
| H A D | pmu.yaml | 4 $id: http://devicetree.org/schemas/arm/samsung/pmu.yaml#
7 title: Samsung Exynos SoC series Power Management Unit (PMU)
18 - samsung,exynos3250-pmu
19 - samsung,exynos4210-pmu
20 - samsung,exynos4412-pmu
21 - samsung,exynos5250-pmu
22 - samsung,exynos5260-pmu
23 - samsung,exynos5410-pmu
24 - samsung,exynos5420-pmu
25 - samsung,exynos5433-pmu
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/arm/rockchip/ |
| H A D | pmu.yaml | 4 $id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml#
7 title: Rockchip Power Management Unit (PMU)
14 The PMU is used to turn on and off different power domains of the SoCs.
22 - rockchip,px30-pmu
23 - rockchip,rk3066-pmu
24 - rockchip,rk3128-pmu
25 - rockchip,rk3288-pmu
26 - rockchip,rk3368-pmu
27 - rockchip,rk3399-pmu
28 - rockchip,rk3568-pmu
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | marvell,dove-pinctrl.txt | 9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
14 Note: pmu* also allows for Power Management functions listed below
18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
21 uart1(rts), pmu*
22 mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
23 uart1(cts), lcd-spi(cs1), pmu*
24 mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
25 mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/perf/ |
| H A D | apm-xgene-pmu.txt | 1 * APM X-Gene SoC PMU bindings
3 This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
4 The following PMU devices are supported:
11 The following section describes the SoC PMU DT node binding.
14 - compatible : Shall be "apm,xgene-pmu" for revision 1 or
15 "apm,xgene-pmu-v2" for revision 2.
19 - reg : First resource shall be the CPU bus PMU resource.
20 - interrupts : Interrupt-specifier for PMU IRQ.
23 - compatible : Shall be "apm,xgene-pmu-l3c".
24 - reg : First resource shall be the L3C PMU resource.
[all …]
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| H A D | fsl-imx-ddr.yaml | 16 - fsl,imx8-ddr-pmu
17 - fsl,imx8m-ddr-pmu
18 - fsl,imx8mq-ddr-pmu
19 - fsl,imx8mm-ddr-pmu
20 - fsl,imx8mn-ddr-pmu
21 - fsl,imx8mp-ddr-pmu
22 - fsl,imx93-ddr-pmu
25 - fsl,imx8mm-ddr-pmu
26 - fsl,imx8mn-ddr-pmu
27 - fsl,imx8mq-ddr-pmu
[all …]
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| H A D | riscv,pmu.yaml | 4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
7 title: RISC-V SBI PMU events
13 The SBI PMU extension allows supervisor software to configure, start and
15 capabilities of performance analysis tools, such as perf, if the SBI PMU
18 The platform must provide information about PMU event to counter mappings
20 Without the event to counter mappings, the SBI PMU extension cannot be used.
22 Platforms should provide information about the PMU event selector values
35 const: riscv,pmu
40 Represents an ONE-to-ONE mapping between a PMU event and the event
77 If a platform directly encodes each raw PMU even
[all...] |
| H A D | marvell-cn10k-tad.yaml | 14 shared on-chip last level cache (LLC). The tad pmu measures the
15 performance of last-level cache. Each tad pmu supports up to eight
18 The DT setup comprises of number of tad blocks, the sizes of pmu
23 const: marvell,cn10k-tad-pmu
36 marvell,tad-pmu-page-size:
37 description: specifies the size of page that the pmu uses
45 - marvell,tad-pmu-page-size
57 compatible = "marvell,cn10k-tad-pmu";
61 marvell,tad-pmu-page-size = <0x1000>;
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| H A D | starfive,jh8100-starlink-pmu.yaml | 4 $id: http://devicetree.org/schemas/perf/starfive,jh8100-starlink-pmu.yaml#
7 title: StarFive JH8100 StarLink PMU
13 StarFive's JH8100 StarLink PMU integrates one or more CPU cores with a
14 shared L3 memory system. The PMU support overflow interrupt, up to
16 counter. StarFive's JH8100 StarLink PMU is accessed via MMIO.
20 const: starfive,jh8100-starlink-pmu
41 pmu@12900000 {
42 compatible = "starfive,jh8100-starlink-pmu";
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| H A D | arm,dsu-pmu.yaml | 5 $id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
8 title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
17 cluster. The PMU enables gathering various statistics on the operation of the
18 DSU. The PMU provides independent 32-bit counters that can count any of the
19 supported events, along with a 64-bit cycle counter. The PMU is accessed via
25 - const: arm,dsu-pmu
27 - const: arm,dsu-110-pmu
28 - const: arm,dsu-pmu
|
| /freebsd/sys/dev/bhnd/cores/pmu/ |
| H A D | bhnd_pmu_if.m | 38 # bhnd(4) PMU interface.
40 # Provides an interface to the PMU hardware found on modern bhnd(4) chipsets.
44 #include <dev/bhnd/cores/pmu/bhnd_pmu_types.h>
134 * Return the current value of a PMU chipctrl register.
136 * @param dev A bhnd(4) PMU device.
137 * @param reg The PMU chipctrl register to be read.
150 * Write @p value with @p mask to a PMU chipctrl register.
152 * @param dev A bhnd(4) PMU device.
153 * @param reg The PMU chipctrl register to be written.
168 * Return the current value of a PMU regulator control register.
[all …]
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| H A D | bhnd_pmu.h | 48 * Return the current value of a PMU chipctrl register.
50 * @param dev A bhnd(4) PMU device.
51 * @param reg The PMU chipctrl register to be read.
65 * Write @p value with @p mask to a PMU chipctrl register.
67 * @param dev A bhnd(4) PMU device.
68 * @param reg The PMU chipctrl register to be written.
83 * Return the current value of a PMU regulator control register.
85 * @param dev A bhnd(4) PMU device.
86 * @param reg The PMU regctrl register to be read.
100 * Write @p value with @p mask to a PMU regulator control register.
[all …]
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| H A D | bhnd_pmureg.h | 40 * Common per-core clock control/status register available on PMU-equipped
82 /* PMU registers */
109 #define BHND_PMU_CAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */
141 #define BHND_PMU_GPIOSEL 0x638 /* pmu rev >= 1 ? */
142 #define BHND_PMU_GPIOEN 0x63C /* pmu rev >= 1 ? */
158 #define BHND_PMU_XTALFREQ 0x66C /* pmu rev >= 10 */
160 /* PMU resource bit position */
163 /* PMU resource number limit */
166 /* PMU chip control0 register */
169 /* PMU chip control1 register */
[all …]
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| /freebsd/sys/arm/arm/ |
| H A D | pmu_fdt.c | 42 #include "pmu.h"
46 {"arm,cortex-a77-pmu", 1},
47 {"arm,cortex-a76-pmu", 1},
48 {"arm,cortex-a75-pmu", 1},
49 {"arm,cortex-a73-pmu", 1},
50 {"arm,cortex-a72-pmu", 1},
51 {"arm,cortex-a65-pmu", 1},
52 {"arm,cortex-a57-pmu", 1},
53 {"arm,cortex-a55-pmu", 1},
54 {"arm,cortex-a53-pmu", 1},
[all …]
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| /freebsd/lib/libpmc/pmu-events/ |
| H A D | README | 2 The contents of this directory allow users to specify PMU events in their
9 tree tools/perf/pmu-events/arch/foo.
12 JSON files, each of which describes a set of PMU events.
14 - The CSV file that maps a specific CPU to its set of PMU events is to
25 The PMU events supported by a CPU model are expected to grouped into topics
33 $ ls tools/perf/pmu-events/arch/x86/Silvermont_core
42 'pmu-events.c', which encodes the two sets of tables:
44 - Set of 'PMU events tables' for all known CPUs in the architecture,
62 'PMU events table'
75 After the 'pmu-events.c' is generated, it is compiled and the resulting
[all …]
|
| /freebsd/share/man/man4/man4.powerpc/ |
| H A D | pmu.4 | 30 .Nm pmu
38 .Cd "device pmu"
43 driver provides support for the Power Management Unit (PMU) found in Apple
48 The Apple PMU controller is a multi-purpose ASIC that provides power
58 Apple KeyLargo PMU
60 Apple K2-KeyLargo PMU
72 .It Va dev.pmu.%d.server_mode
75 .It Va dev.pmu.%d.batteries.%d.present
77 .It Va dev.pmu.%d.batteries.%d.charging
79 .It Va dev.pmu.%d.batteries.%d.charge
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/power/ |
| H A D | rockchip-io-domain.yaml | 49 - rockchip,px30-pmu-io-voltage-domain
56 - rockchip,rk3368-pmu-io-voltage-domain
58 - rockchip,rk3399-pmu-io-voltage-domain
59 - rockchip,rk3568-pmu-io-voltage-domain
61 - rockchip,rv1108-pmu-io-voltage-domain
62 - rockchip,rv1126-pmu-io-voltage-domain
71 - $ref: "#/$defs/px30-pmu"
78 - $ref: "#/$defs/rk3368-pmu"
80 - $ref: "#/$defs/rk3399-pmu"
81 - $ref: "#/$defs/rk3568-pmu"
[all …]
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| H A D | rockchip-io-domain.txt | 35 - "rockchip,px30-pmu-io-voltage-domain" for px30 pmu-domains
41 - "rockchip,rk3368-pmu-io-voltage-domain" for rk3368 pmu-domains
43 - "rockchip,rk3399-pmu-io-voltage-domain" for rk3399 pmu-domains
45 - "rockchip,rv1108-pmu-io-voltage-domain" for rv1108 pmu-domains
65 Possible supplies for PX30 pmu-domains:
107 Possible supplies for rk3368 pmu-domains:
108 - pmu-supply: The supply connected to PMUIO_VDD.
117 Possible supplies for rk3399 pmu-domains:
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| /freebsd/sys/contrib/device-tree/Bindings/soc/dove/ |
| H A D | pmu.txt | 1 Device Tree bindings for Marvell PMU
4 - compatible: value should be "marvell,dove-pmu".
7 - reg: two base addresses and sizes of the PM controller and PMU.
8 - interrupts: single interrupt number for the PMU interrupt
9 - interrupt-controller: must be specified as the PMU itself is an
27 - marvell,pmu_pwr_mask: specifies the mask value for PMU power register
28 - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register
29 - resets: points to the reset manager (PMU node) and reset index.
33 pmu: power-management@d0000 {
34 compatible = "marvell,dove-pmu";
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/regulator/ |
| H A D | qcom,qca6390-pmu.yaml | 4 $id: http://devicetree.org/schemas/regulator/qcom,qca6390-pmu.yaml#
7 title: Qualcomm Technologies, Inc. QCA6390 PMU Regulators
14 are powered by the Power Management Unit (PMU) that takes inputs from the
20 - qcom,qca6390-pmu
21 - qcom,wcn6855-pmu
22 - qcom,wcn7850-pmu
65 description: GPIO line enabling the ATH11K WLAN module supplied by the PMU
69 description: GPIO line enabling the Bluetooth module supplied by the PMU
82 LDO outputs of the PMU
101 const: qcom,qca6390-pmu
[all …]
|
| /freebsd/sbin/devd/ |
| H A D | apple.conf | 6 match "system" "PMU";
14 match "system" "PMU";
23 match "system" "PMU";
32 match "system" "PMU";
43 match "system" "PMU";
50 match "system" "PMU";
58 match "system" "PMU";
67 match "system" "PMU";
75 match "system" "PMU";
|
| H A D | devd.conf.5 | 512 .It Li PMU Ta Ta Ta
514 .It Li PMU Ta Li "AC" Ta Ta
516 .It Li PMU Ta Li "AC" Ta Li overvoltage Ta
518 .It Li PMU Ta Li "AC" Ta Li plugged Ta
520 .It Li PMU Ta Li "AC" Ta Li unplugged Ta
522 .It Li PMU Ta Li Battery Ta Ta
523 .It Li PMU Ta Li Battery Ta absent Ta
525 .It Li PMU Ta Li Battery Ta charged Ta
527 .It Li PMU Ta Li Battery Ta charging Ta
529 .It Li PMU Ta Li Battery Ta disconnected Ta
[all …]
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| /freebsd/sys/contrib/xen/ |
| H A D | pmu.h | 28 #include "arch-x86/pmu.h"
42 * @cmd == XENPMU_* (PMU operation)
46 #define XENPMU_mode_get 0 /* Also used for getting PMU version */
72 /* PMU modes:
73 * - XENPMU_MODE_OFF: No PMU virtualization
86 * PMU features:
102 * Shared PMU data between hypervisor and PV(H) domains.
104 * The hypervisor fills out this structure during PMU interrupt and sends an
108 * by both the hypervisor and the guest (see arch-$arch/pmu.h).
130 xen_pmu_arch_t pmu; member
|