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/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-power.dtsi11 fsl,pmcdr-mask = <0x00000080>;
14 fsl,pmcdr-mask = <0x00000040>;
17 fsl,pmcdr-mask = <0x00000020>;
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dpmc.yaml26 which will be ORed into PMCDR upon suspend, and cleared from PMCDR upon
86 Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
/linux/include/linux/fsl/
H A Dguts.h77 u32 pmcdr; /* 0x.008c - 4Power management clock disable member