Home
last modified time | relevance | path

Searched full:pll4 (Results 1 – 25 of 49) sorted by relevance

12

/linux/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun9i-a80-pll4-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-pll4-clk.yaml#
20 const: allwinner,sun9i-a80-pll4-clk
44 compatible = "allwinner,sun9i-a80-pll4-clk";
47 clock-output-names = "pll4";
H A Dqcom,gcc-ipq8064.yaml34 - description: PLL4 from LCC
41 - const: pll4
66 clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
67 clock-names = "pxo", "cxo", "pll4";
H A Dallwinner,sun9i-a80-apb0-clk.yaml50 clocks = <&osc24M>, <&pll4>;
59 clocks = <&osc24M>, <&pll4>;
H A Dallwinner,sun9i-a80-cpus-clk.yaml48 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
H A Dallwinner,sun9i-a80-ahb-clk.yaml48 clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
H A Dallwinner,sun9i-a80-gt-clk.yaml48 clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
H A Dallwinner,sun4i-a10-ve-clk.yaml51 clocks = <&pll4>;
H A Dqcom,gcc-mdm9615.yaml31 - description: PLL4 from LLC
H A Dallwinner,sun4i-a10-mmc-clk.yaml82 clocks = <&osc24M>, <&pll4>;
H A Dqcom,gcc-apq8064.yaml48 - const: pll4
/linux/drivers/clk/qcom/
H A Dlcc-ipq806x.c26 static struct clk_pll pll4 = { variable
35 .name = "pll4",
401 [PLL4] = &pll4.clkr,
450 /* Configure the rate of PLL4 if the bootloader hasn't already */ in lcc_ipq806x_probe()
453 clk_pll_configure_sr(&pll4, regmap, &pll4_config, true); in lcc_ipq806x_probe()
454 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_ipq806x_probe()
H A Dlcc-msm8960.c29 static struct clk_pll pll4 = { variable
38 .name = "pll4",
397 [PLL4] = &pll4.clkr,
470 /* Use the correct frequency plan depending on speed of PLL4 */ in lcc_msm8960_probe()
481 /* Enable PLL4 source on the LPASS Primary PLL Mux */ in lcc_msm8960_probe()
/linux/Documentation/devicetree/bindings/sound/
H A Dti,j721e-cpb-audio.yaml19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
25 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
34 PLL4 ---> PLL4_HSDIV0 ---> MCASP0_AUXCLK ---> McASP0.auxclk
H A Dti,j721e-cpb-ivi-audio.yaml24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
28 Note: the same PLL4 and PLL15 is used by the audio support on the CPB!
31 PLL4 ---> PLL4_HSDIV0 ---> MCASP10_AUXCLK ---> McASP10.auxclk
/linux/drivers/clk/sunxi/
H A Dclk-sun9i-core.c18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
19 * PLL4 rate is calculated as follows
82 pr_err("Could not get registers for a80-pll4-clk: %pOFn\n", in sun9i_a80_pll4_setup()
90 CLK_OF_DECLARE(sun9i_a80_pll4, "allwinner,sun9i-a80-pll4-clk", sun9i_a80_pll4_setup);
H A Dclk-sun9i-cpus.c59 /* apply pre-divider first if parent is pll4 */ in sun9i_a80_cpus_clk_recalc_rate()
83 /* calculate pre-divider if parent is pll4 */ in sun9i_a80_cpus_clk_round()
/linux/drivers/clk/imx/
H A Dclk-imx8ulp.c37 static const char * const hifi_sels[] = { "frosc", "pll4", "pll4_pfd0", "sosc",
40 "pll4", "pll4", "pll4", "pll4", };
251 clks[IMX8ULP_CLK_PLL4] = imx_clk_hw_pllv4(IMX_PLLV4_IMX8ULP, "pll4", "pll4_pre_sel", base + 0x600); in imx8ulp_clk_cgc2_init()
252 clks[IMX8ULP_CLK_PLL4_VCODIV] = imx_clk_hw_divider("pll4_vcodiv", "pll4", base + 0x604, 0, 6); in imx8ulp_clk_cgc2_init()
/linux/include/dt-bindings/clock/
H A Dqcom,lcc-ipq806x.h9 #define PLL4 0 macro
H A Dqcom,lcc-msm8960.h9 #define PLL4 0 macro
H A Dstm32mp13-clks.h22 #define PLL4 9 macro
/linux/drivers/clk/renesas/
H A Dr9a09g077-cpg.c121 static const char * const sel_clk_pll4[] = { ".loco", ".pll4" };
132 DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 1, 96),
H A Dr8a774b1-cpg-mssr.c60 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
259 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
H A Dr8a774e1-cpg-mssr.c62 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
271 * MD EXTAL PLL0 PLL1 PLL2 PLL3 PLL4 OSC
H A Dr8a77965-cpg-mssr.c63 DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
288 * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-odyssey.dts41 assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */

12