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/linux/drivers/net/fddi/skfp/
H A Dpcmplc.c110 * this register in the PLC-S controls the scrambling parameters
122 * this register in the PLC-S controls the scrambling parameters
149 * PLC timing parameter
157 int timer ; /* relative plc timer address */
381 memset((char *)&phy->plc,0,sizeof(struct s_plc)) ; in pcm_init()
382 phy->plc.p_state = PS_OFF ; in pcm_init()
415 int rev ; /* Revision of PLC-x */ in plc_init()
419 outpw(PLC(p,PL_CNTRL_B),0) ; in plc_init()
420 outpw(PLC(p,PL_CNTRL_B),PL_PCM_STOP) ; in plc_init()
421 outpw(PLC(p,PL_CNTRL_A),0) ; in plc_init()
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H A Ddrvfbi.c230 u_short st = inpw(PLC(PB,PL_INTR_EVENT)) ; in plc1_irq()
241 u_short st = inpw(PLC(PA,PL_INTR_EVENT)) ; in plc2_irq()
433 void pcm_state_change(struct s_smc *smc, int plc, int p_state) in pcm_state_change() argument
440 DRV_PCM_STATE_CHANGE(smc,plc,p_state) ; in pcm_state_change()
/linux/drivers/net/fddi/skfp/h/
H A Dsupern_2.h15 PLC Physical Layer
540 #define FM_PLC_BIST_DONE 0x0002 /* internal PLC Bist is done */
571 #define FM_MENPLCCST 0x0200 /* Ena Counter Segm test in PLC blck */
702 * defines for PLC (Am79C864)
706 * PLC read/write (r/w) registers
763 * PLC control register A (PL_CNTRL_A: log. addr. 0x00)
765 * counter interrupt frequency, PLC data path config. and Built In Self Test.
773 #define PL_FOT_OFF 0x0040 /* assertion of /FOTOFF pin of PLC */
784 * PLC control register B (PL_CNTRL_B: log. addr. 0x01)
826 * PLC control register C (PL_CNTRL_C: log. addr. 0x0a)
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H A Dcmtdef.h20 #define AMDPLC /* if Amd PLC chip used */
110 * because the MAC output goes through the 2. PLC
113 #define PS 0 /* Internal PLC which is the same as PA */
450 * PLC state table
561 void pcm_state_change(struct s_smc *smc, int plc, int p_state);
/linux/drivers/pci/controller/dwc/
H A Dpcie-designware.c741 u32 lnkcap, lwsc, plc; in dw_pcie_link_set_max_link_width() local
748 plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); in dw_pcie_link_set_max_link_width()
749 plc &= ~PORT_LINK_FAST_LINK_MODE; in dw_pcie_link_set_max_link_width()
750 plc &= ~PORT_LINK_MODE_MASK; in dw_pcie_link_set_max_link_width()
757 plc |= PORT_LINK_MODE_1_LANES; in dw_pcie_link_set_max_link_width()
761 plc |= PORT_LINK_MODE_2_LANES; in dw_pcie_link_set_max_link_width()
765 plc |= PORT_LINK_MODE_4_LANES; in dw_pcie_link_set_max_link_width()
769 plc |= PORT_LINK_MODE_8_LANES; in dw_pcie_link_set_max_link_width()
776 dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); in dw_pcie_link_set_max_link_width()
/linux/include/sound/
H A Dwm0010.h5 * Copyright 2012 Wolfson Microelectronics PLC.
H A Dwm2000.h5 * Copyright 2010 Wolfson Microelectronics. PLC.
H A Dwm8955.h5 * Copyright 2009 Wolfson Microelectronics PLC.
H A Dwm9081.h5 * Copyright 2009 Wolfson Microelectronics. PLC.
H A Dwm9090.h5 * Copyright 2009, 2010 Wolfson Microelectronics. PLC.
H A Dwm5100.h5 * Copyright 2011 Wolfson Microelectronics. PLC.
H A Dwm8993.h5 * Copyright 2009 Wolfson Microelectronics. PLC.
/linux/sound/soc/codecs/
H A Dwm8728.h5 * Copyright 2008 Wolfson Microelectronics plc
H A Dwm5102.h5 * Copyright 2012 Wolfson Microelectronics plc
H A Dwm5110.h5 * Copyright 2012 Wolfson Microelectronics plc
H A Dwm8997.h5 * Copyright 2012 Wolfson Microelectronics plc
H A Dwm8350.h5 * Copyright 2008 Wolfson Microelectronics PLC.
H A Dwm8776.h5 * Copyright 2009 Wolfson Microelectronics plc
H A Dwm8770.h5 * Copyright 2010 Wolfson Microelectronics plc
/linux/drivers/mfd/
H A Dwm8994.h5 * Copyright 2011 Wolfson Microelectronics PLC.
H A Darizona.h5 * Copyright 2012 Wolfson Microelectronics plc
/linux/include/linux/mfd/wm8350/
H A Dwdt.h5 * Copyright 2007, 2008 Wolfson Microelectronics PLC
/linux/drivers/regulator/
H A Ddummy.h5 * Copyright 2010 Wolfson Microelectronics PLC.
/linux/arch/arm/mach-s3c/
H A Dcrag6410.h4 * Copyright 2011 Wolfson Microelectronics plc
/linux/include/linux/mfd/
H A Dwm8400.h5 * Copyright 2008 Wolfson Microelectronics plc

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