Lines Matching full:plc
15 PLC Physical Layer
540 #define FM_PLC_BIST_DONE 0x0002 /* internal PLC Bist is done */
571 #define FM_MENPLCCST 0x0200 /* Ena Counter Segm test in PLC blck */
702 * defines for PLC (Am79C864)
706 * PLC read/write (r/w) registers
763 * PLC control register A (PL_CNTRL_A: log. addr. 0x00)
765 * counter interrupt frequency, PLC data path config. and Built In Self Test.
773 #define PL_FOT_OFF 0x0040 /* assertion of /FOTOFF pin of PLC */
784 * PLC control register B (PL_CNTRL_B: log. addr. 0x01)
826 * PLC control register C (PL_CNTRL_C: log. addr. 0x0a)
827 * It contains the scrambling control registers (PLC-S only)
861 * PLC status register A (PL_STATUS_A: log. addr. 0x10)
875 #define PLC_REVISION_A 0x0000 /* revision bits for PLC */
876 #define PLC_REVISION_S 0xf800 /* revision bits for PLC-S */
877 #define PLC_REV_SN3 0x7800 /* revision bits for PLC-S in IFCP */
903 * PLC status register B (PL_STATUS_B: log. addr. 0x11)
949 * PLC interrupt event register (PL_INTR_EVENT: log. addr. 0x17)
951 * It is used by the PLC to report events to the node processor.
971 * The PLC interrupt mask register (PL_INTR_MASK: log. addr. 0x02) constr. is
1003 * PLC Timing Parameters
1017 #define PLC_BIST 0x6ecd /* BIST signature for PLC */
1018 #define PLCS_BIST 0x5b6b /* BIST signature for PLC-S */