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/linux/include/dt-bindings/clock/
H A Drk3036-cru.h64 #define PCLK_I2C0 332 macro
H A Drk3188-cru-common.h88 #define PCLK_I2C0 336 macro
H A Drk3128-cru.h103 #define PCLK_I2C0 332 macro
H A Drk3228-cru.h102 #define PCLK_I2C0 332 macro
H A Drk3368-cru.h116 #define PCLK_I2C0 332 macro
H A Drk3308-cru.h181 #define PCLK_I2C0 202 macro
H A Drk3288-cru.h124 #define PCLK_I2C0 332 macro
H A Drk3328-cru.h136 #define PCLK_I2C0 205 macro
H A Dpx30-cru.h157 #define PCLK_I2C0 334 macro
H A Drockchip,rv1126-cru.h46 #define PCLK_I2C0 33 macro
H A Drockchip,rk3576-cru.h511 #define PCLK_I2C0 493 macro
H A Drockchip,rk3588-cru.h642 #define PCLK_I2C0 627 macro
H A Drk3568-cru.h58 #define PCLK_I2C0 45 macro
/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-rk3x.yaml136 clocks = <&cru PCLK_I2C0>;
/linux/drivers/clk/rockchip/
H A Dclk-rk3036.c420 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
H A Dclk-rk3128.c507 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
H A Dclk-rk3228.c601 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
H A Dclk-rk3188.c496 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
H A Dclk-rk3328.c771 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3328_CLKGATE_CON(15), 10, GFLAGS),
H A Dclk-rk3368.c702 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 2, GFLAGS),
H A Dclk-rv1126.c305 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
H A Dclk-rk3308.c870 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 15, GFLAGS),
H A Dclk-px30.c851 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 10, GFLAGS),
H A Dclk-rk3288.c685 GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
/linux/arch/arm/boot/dts/rockchip/
H A Drk3xxx.dtsi313 clocks = <&cru PCLK_I2C0>;

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