Home
last modified time | relevance | path

Searched full:pcie (Results 1 – 25 of 1479) sorted by relevance

12345678910>>...60

/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dfsl,imx6q-pcie-common.yaml4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
7 title: Freescale i.MX6 PCIe RC/EP controller
14 Generic Freescale i.MX PCIe Root Port and Endpoint controller
29 fsl,imx7d-pcie-phy:
31 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
32 required properties for imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie,
33 and imx8mq-pcie-ep.
39 imx6sx-pcie, imx6sx-pcie-ep, to PCIE_PHY power domain for
40 imx7d-pcie, imx7d-pcie-ep, imx8mq-pcie and imx8mq-pcie-ep.
42 for imx6sx-pcie and imx6sx-pcie-ep.
[all …]
H A Dfsl,imx6q-pcie.yaml4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
7 title: Freescale i.MX6 PCIe host controller
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
25 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie
27 - fsl,imx6qp-pcie
28 - fsl,imx7d-pcie
29 - fsl,imx8mq-pcie
[all …]
H A Dqcom,pcie.yaml4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
21 - qcom,pcie-apq8064
22 - qcom,pcie-apq8084
23 - qcom,pcie-ipq4019
24 - qcom,pcie-ipq6018
25 - qcom,pcie-ipq8064
26 - qcom,pcie-ipq8064-v2
27 - qcom,pcie-ipq8074
[all …]
H A Dqcom,pcie-ep.yaml4 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
7 title: Qualcomm PCIe Endpoint Controller
16 - qcom,sa8775p-pcie-ep
17 - qcom,sdx55-pcie-ep
18 - qcom,sm8450-pcie-ep
20 - const: qcom,sdx65-pcie-ep
21 - const: qcom,sdx55-pcie-ep
27 - description: DesignWare PCIe registers
67 - description: PCIe Global interrupt
68 - description: PCIe Doorbell interrupt
[all …]
H A Drcar-pci.txt1 * Renesas R-Car PCIe interface
4 compatible: "renesas,pcie-r8a7742" for the R8A7742 SoC;
5 "renesas,pcie-r8a7743" for the R8A7743 SoC;
6 "renesas,pcie-r8a7744" for the R8A7744 SoC;
7 "renesas,pcie-r8a774a1" for the R8A774A1 SoC;
8 "renesas,pcie-r8a774b1" for the R8A774B1 SoC;
9 "renesas,pcie-r8a774c0" for the R8A774C0 SoC;
10 "renesas,pcie-r8a7779" for the R8A7779 SoC;
11 "renesas,pcie-r8a7790" for the R8A7790 SoC;
12 "renesas,pcie-r8a7791" for the R8A7791 SoC;
[all …]
H A Dlayerscape-pci.txt1 Freescale Layerscape PCIe controller
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
10 register available in the Freescale PCIe controller register set,
11 which can allow determining the underlying DesignWare PCIe controller version
17 "fsl,ls1021a-pcie"
18 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
19 "fsl,ls2088a-pcie"
20 "fsl,ls1088a-pcie"
21 "fsl,ls1046a-pcie"
[all …]
H A Dfsl,imx6q-pcie-ep.yaml4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
7 title: Freescale i.MX6 PCIe Endpoint controller
14 This PCIe controller is based on the Synopsys DesignWare PCIe IP and
15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
22 - fsl,imx8mm-pcie-ep
23 - fsl,imx8mq-pcie-ep
24 - fsl,imx8mp-pcie-ep
25 - fsl,imx95-pcie-ep
30 - description: PCIe bridge clock.
31 - description: PCIe bus clock.
[all …]
H A Drcar-pci-host.yaml8 title: Renesas R-Car PCIe Host
20 - const: renesas,pcie-r8a7779 # R-Car H1
23 - renesas,pcie-r8a7742 # RZ/G1H
24 - renesas,pcie-r8a7743 # RZ/G1M
25 - renesas,pcie-r8a7744 # RZ/G1N
26 - renesas,pcie-r8a7790 # R-Car H2
27 - renesas,pcie-r8a7791 # R-Car M2-W
28 - renesas,pcie-r8a7793 # R-Car M2-N
29 - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
32 - renesas,pcie-r8a774a1 # RZ/G2M
[all …]
H A Dfsl,imx6q-pcie.txt1 * Freescale i.MX6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in designware-pcie.txt.
8 - "fsl,imx6q-pcie"
9 - "fsl,imx6sx-pcie",
10 - "fsl,imx6qp-pcie"
11 - "fsl,imx7d-pcie"
12 - "fsl,imx8mq-pcie"
13 - reg: base address and length of the PCIe controller
37 - vpcie-supply: Should specify the regulator in charge of PCIe port power.
[all …]
H A Dfsl,layerscape-pcie.yaml4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
7 title: Freescale Layerscape PCIe Root Complex(RC) controller
13 This PCIe RC controller is based on the Synopsys DesignWare PCIe IP
19 register available in the Freescale PCIe controller register set,
20 which can allow determining the underlying DesignWare PCIe controller version
27 - fsl,ls1012a-pcie
28 - fsl,ls1021a-pcie
29 - fsl,ls1028a-pcie
30 - fsl,ls1043a-pcie
31 - fsl,ls1046a-pcie
[all …]
H A Dqcom,pcie.txt7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sc8180x" for sc8180x
16 - "qcom,pcie-sdm845" for sdm845
[all …]
H A Dbrcm,iproc-pcie.yaml4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
7 title: Broadcom iProc PCIe controller with the platform bus interface
22 - brcm,iproc-pcie
25 - brcm,iproc-pcie-paxb-v2
27 - brcm,iproc-pcie-paxc
29 - brcm,iproc-pcie-paxc-v2
34 Base address and length of the PCIe controller I/O register space
47 - const: pcie-phy
51 brcm,pcie-ob:
57 brcm,pcie-ob-axi-offset:
[all …]
H A Dmvebu-pci.txt1 * Marvell EBU PCIe interfaces
6 marvell,armada-370-pcie
7 marvell,armada-xp-pcie
8 marvell,dove-pcie
9 marvell,kirkwood-pcie
15 - ranges: ranges describing the MMIO registers to control the PCIe
17 the memory and I/O regions of each PCIe interface.
28 registers of this PCIe interface, from the base of the internal
46 * s is the PCI slot that corresponds to this PCIe interface
58 PCIe interface, having the following mandatory properties:
[all …]
H A Dnvidia,tegra20-pcie.txt1 NVIDIA Tegra PCIe controller
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
11 contain BPMP phandle and PCIe power partition ID. This is required only
71 - "default": active state, puts PCIe I/O out of deep power down state
72 - "idle": puts PCIe I/O into deep power down state
79 - pcie
[all …]
H A Dpci-keystone.txt1 TI Keystone PCIe interface
4 hardware version 3.65. It shares common functions with the PCIe DesignWare
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
24 (required if the compatible is "ti,keystone-pcie")
26 (required if the compatible is "ti,am654-pcie-rc".
28 ti,syscon-pcie-id : phandle to the device control module required to set device
[all …]
H A Daxis,artpec6-pcie.txt1 * Axis ARTPEC-6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
21 - axis,syscon-pcie: A phandle pointing to the ARTPEC-6 system controller,
26 pcie@f8050000 {
[all …]
H A Dmediatek-pcie.txt1 MediaTek Gen2 PCIe controller
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 "mediatek,mt7629-pcie"
10 "airoha,en7523-pcie"
22 - free_ck :for reference clock of PCIe subsys
34 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
48 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
[all …]
H A Dbrcm,iproc-pcie.txt1 * Broadcom iProc PCIe controller with the platform bus interface
5 "brcm,iproc-pcie" for the first generation of PAXB based controller,
7 "brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
9 "brcm,iproc-pcie-paxc" for the first generation of PAXC based
11 "brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
15 - reg: base address and length of the PCIe controller I/O register space
18 mapping of the PCIe interface to interrupt numbers
27 - phys: phandle of the PCIe PHY device
28 - phy-names: must be "pcie-phy"
34 - brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done
[all …]
H A Dti,j721e-pci-host.yaml8 title: TI J721E PCI Host (PCIe Wrapper)
16 - const: ti,j721e-pcie-host
17 - const: ti,j784s4-pcie-host
18 - description: PCIe controller in AM64
20 - const: ti,am64-pcie-host
21 - const: ti,j721e-pcie-host
22 - description: PCIe controller in J7200
24 - const: ti,j7200-pcie-host
25 - const: ti,j721e-pcie-host
26 - description: PCIe controller in J722S
[all …]
H A Damlogic,meson-pcie.txt1 Amlogic Meson AXG DWC PCIE SoC controller
3 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
4 It shares common functions with the PCIe DesignWare core driver and
6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
13 - "amlogic,axg-pcie" for AXG SoC Family
14 - "amlogic,g12a-pcie" for G12A SoC Family
21 - "config" PCIe configuration space
22 - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
25 - "pclk" PCIe GEN 100M PLL clock
27 - "general" PCIe Phy clock
[all …]
H A Damlogic,axg-pcie.yaml4 $id: http://devicetree.org/schemas/pci/amlogic,axg-pcie.yaml#
7 title: Amlogic Meson AXG DWC PCIe SoC controller
13 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
17 - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
19 # We need a select here so we don't match all nodes with 'snps,dw-pcie'
24 - amlogic,axg-pcie
25 - amlogic,g12a-pcie
33 - amlogic,axg-pcie
34 - amlogic,g12a-pcie
35 - const: snps,dw-pcie
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
22 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
23 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
24 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
25 - qcom,sdm845-qhp-pcie-phy
[all …]
H A Dqcom,qmp-pcie-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
7 title: Qualcomm QMP PHY controller (PCIe)
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,ipq6018-qmp-pcie-phy
20 - qcom,ipq8074-qmp-gen3-pcie-phy
21 - qcom,ipq8074-qmp-pcie-phy
22 - qcom,msm8998-qmp-pcie-phy
23 - qcom,sc8180x-qmp-pcie-phy
24 - qcom,sdm845-qhp-pcie-phy
25 - qcom,sdm845-qmp-pcie-phy
[all …]
H A Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
15 ports (e.g. PCIe) and the lanes.
49 - avdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
55 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
83 For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
86 For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
105 PCIe pad:
114 - "phy": reset for the PCIe UPHY block
148 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
149 - functions: "pcie", "usb3-ss"
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_pcie.h41 * This header file provide API for the HAL driver of the pcie port, the driver
50 * - PCIe transactions generation and reception (except interrupts as mentioned
55 * through the fabric toward the PCIe port. This API provides management
60 * - PCIe Port Management: both link and port power management features can be
61 * managed using the PCI/PCIe standard power management and PCIe capabilities
63 * - PCIe link and protocol error handling: the feature can be managed using
64 * the Advanced Error Handling PCIe capability registers.
89 * - Enable pcie core RAM parity
90 * - Enable pcie core AXI parity
104 * AL_TRUE, // enable pcie port RAM parity
[all …]

12345678910>>...60