Lines Matching full:pcie
41 * This header file provide API for the HAL driver of the pcie port, the driver
50 * - PCIe transactions generation and reception (except interrupts as mentioned
55 * through the fabric toward the PCIe port. This API provides management
60 * - PCIe Port Management: both link and port power management features can be
61 * managed using the PCI/PCIe standard power management and PCIe capabilities
63 * - PCIe link and protocol error handling: the feature can be managed using
64 * the Advanced Error Handling PCIe capability registers.
89 * - Enable pcie core RAM parity
90 * - Enable pcie core AXI parity
104 * AL_TRUE, // enable pcie port RAM parity
105 * AL_TRUE, // enable pcie port AXI parity
117 * - once the port configured, we can start PCIe link:
135 * - we assume using ECAM method, in this method, the software issues pcie Cfg
136 * access by accessing the ECAM memory space of the pcie port. For example, to
164 * PCIe Core revision IDs:
187 * PCIe AER uncorrectable error bits
218 * PCIe AER correctable error bits
269 * al_pcie_port: data structure used by the HAL to handle a specific pcie port.
327 /** PCIe capabilities that supported by a specific port */
337 /** PCIe link related parameters */
344 /** PCIe gen2 link parameters */
351 /** PCIe gen 3 standard per lane equalization parameters */
359 /** PCIe gen 3 equalization parameters */
380 * the PCIe port. This resource includes the PCIe TLP headers coming on the PCIe
382 * - Inbound Non-posted, which are PCIe Reads as well as PCIe Config Cycles
383 * - Inbound Posted, i.e. PCIe Writes
425 * PCIe Ack/Nak Latency and Replay timers
439 * Description: SRIS is PCI SIG ECN, that enables the two peers on a given PCIe
441 * clock and requires inserting PCIe SKP symbols on the link in faster frequency
442 * that original PCIe spec
473 /** PCIe port configuration parameters
543 /** PCIe link status */
551 /** PCIe lane status */
558 * PCIe MSIX capability configuration parameters
571 /** PCIE AER capability parameters */
602 /********************************** PCIe API **********************************/
605 /*************************** PCIe Initialization API **************************/
608 * Initializes a PCIe port handle structure.
625 * Initializes a PCIe pf handle structure
627 * @param pcie_port pcie port handle
638 * @param pcie_port pcie port handle
643 /************************** Pre PCIe Port Enable API **************************/
646 * @brief set current pcie operating mode (root complex or endpoint)
650 * @param pcie_port pcie port handle
651 * @param mode pcie operating mode
662 * @param pcie_port pcie port handle
673 * @param pcie_port pcie port handle
678 * - exposed on a given PCIe Endpoint port
679 * - PCIe rev1/rev2 supports only single Endpoint
680 * - PCIe rev3 can support up to 4
690 * @param pcie_port pcie port handle
699 /** return PCIe operating mode
700 * @param pcie_port pcie port handle
707 * PCIe AXI quality of service configuration
710 * Initialized PCIe port handle
721 /**************************** PCIe Port Enable API ****************************/
724 * Enable PCIe unit (deassert reset)
728 * @param pcie_port pcie port handle
734 /** Disable PCIe unit (assert reset)
736 * @param pcie_port pcie port handle
746 * @param pcie_port pcie port handle
756 * @param pcie_port pcie port handle
761 /*************************** PCIe Configuration API ***************************/
764 * @brief configure pcie port (mode, link params, etc..)
767 * @param pcie_port pcie port handle
779 * @param pcie_pf pcie pf handle
788 /************************** PCIe Link Operations API **************************/
791 * @brief start pcie link
794 * @param pcie_port pcie port handle
801 * @brief stop pcie link
803 * @param pcie_port pcie port handle
810 * @brief check if pcie link is started
812 * @param pcie_port pcie port handle
820 * @param pcie_port pcie port handle
824 * functionality where both sides of the PCIe agrees to disable the link
833 * @param pcie_port pcie port handle
844 * @param pcie_port pcie port handle
855 * pcie port handle
857 * PCIe lane
874 * @param pcie_port pcie port handle
888 * @param pcie_port pcie port handle
899 * @param pcie_port pcie port handle
914 * @brief configure pcie port axi snoop
915 * This enable the inbound PCIe posted write data or the Read completion data to
918 * @param pcie_port pcie port handle
932 * on the PCIe ports by writing to part of the processor memory space marked by
938 * @param pcie_pf pcie pf handle
949 * @param pcie_pf pcie pf handle
960 * @param pcie_pf PCIe pf handle
965 * the PCIe Core specifications
983 * @param pcie_port pcie port handle
994 * @param pcie_port pcie port handle
1008 * @param pcie_port pcie port handle
1020 * @param pcie_port pcie port handle
1022 * downstream of the PCIE instance.
1036 * @param pcie_port pcie port handle
1043 * @param pcie_port pcie port handle
1055 /** decoding of the PCIe TLP Type as appears on the wire */
1084 * on the PCIe TLP
1089 * For Alpine V1 (PCIe rev1): only bits [39:0] are valid
1090 * For Alpine V2 (PCIe rev2/rev3): only bits [47:0] are valid
1112 * PCIe TLP type
1117 * PCIe frame header attr field.
1128 * PCIe Message code
1136 * CFG Shift Mode. This is useful for CFG transactions where the PCIe
1164 * from the PCIe core
1165 * - AL_FALSE: no function number is taken from PCIe core
1205 * @param pcie_port pcie port handle
1216 * @param pcie_port pcie port handle
1231 * This is an EP feature, enabling PCIe IO transaction to be captured if it fits
1235 * @param pcie_port pcie port handle
1256 * @param pcie_pf pcie pf handle
1263 * @param pcie_pf pcie pf handle
1275 * @param pcie_pf pcie pf handle
1283 * @param pcie_pf pcie pf handle
1293 * @param pcie_pf pcie pf handle
1300 * @param pcie_pf pcie pf handle
1309 * @param pcie_pf pcie pf handle
1319 * @param pcie_pf pcie pf handle
1327 * @param pcie_pf pcie pf handle
1336 * @param pcie_pf pcie pf handle
1345 * @param pcie_port pcie port handle
1355 * @param pcie_port pcie port handle
1364 * @param pcie_port pcie port handle
1374 * @param pcie_port pcie port handle
1391 * @param pcie_port pcie port handle
1399 * @param pcie_port pcie port handle
1412 * @param pcie_port pcie port handle
1420 * @param pcie_port pcie port handle