Searched full:p5600 (Results 1 – 12 of 12) sorted by relevance
30 | +----+------|- MIPS P5600 cores48 to create a clock for the MIPS P5600 cores, the embedded DDR controller,78 clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
33 | +----+------|- MIPS P5600 cores
52 #define MODULE_PROC_FAMILY "P5600 "
830 /* Config6 feature bits for proAptiv/P5600 */
15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
62 peripheral IP-cores with RAM controller and with MIPS P5600 cores on
163 cflags-$(CONFIG_CPU_P5600) += $(call cc-option,-march=p5600,-march=mips32r5) \
1656 /* P5600 */1939 mipspmu.name = "mips/P5600"; in init_hw_perf_events()
1412 __cpu_name[cpu] = "MIPS P5600"; in cpu_probe_mips()
996 * P5600 generates GPSI on guest MTC0 LLAddr. in kvm_vz_gpsi_cop0()