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/linux/Documentation/devicetree/bindings/mtd/
H A Dbrcm,brcmnand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom STB NAND Controller
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
27 -- Additional SoC-specific NAND controller properties --
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H A Dmarvell,nand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell NAND Flash Controller (NFC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 - items:
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
18 - enum:
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/linux/Documentation/driver-api/
H A Dmtdnand.rst2 MTD NAND Driver Programming Interface
10 The generic NAND driver supports almost all NAND and AG-AND based chips
15 board drivers or filesystem drivers suitable for NAND devices.
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
45 These functions are exported and provide the interface to the NAND
48 - [GENERIC]
53 - [DEFAULT]
55 Default functions provide hardware related functionality which is
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/linux/drivers/mtd/nand/raw/
H A Dfsmc_nand.c1 // SPDX-License-Identifier: GPL-2.0
5 * Driver for NAND portions
11 * Based on drivers/mtd/nand/nomadik_nand.c (removed in v3.8)
20 #include <linux/dma-direction.h>
21 #include <linux/dma-mapping.h>
29 #include <linux/mtd/nand-ecc-sw-hamming.h>
37 #include <mtd/mtd-abi.h>
61 /* fsmc controller registers for NAND flash */
99 * TOUDEL = 7ns (Output delay from the flip-flops to the board)
120 * struct fsmc_nand_data - structure for FSMC NAND device state
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H A Dsunxi_nand.c1 // SPDX-License-Identifier: GPL-2.0+
6 * https://github.com/yuq/sunxi-nfc-mtd
9 * https://github.com/hno/Allwinner-Info
16 #include <linux/dma-mapping.h>
70 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
107 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
161 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
163 * @cs: the NAND CS id used to communicate with a NAND Chip
164 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC
172 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
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H A Dcadence-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence NAND flash controller driver
12 #include <linux/dma-mapping.h>
26 * - PIO - can work in master or slave DMA
27 * - CDMA - needs Master DMA for accessing command descriptors.
28 * - Generic mode - can use only slave DMA.
31 * on NAND flash memory. Driver uses CDMA mode for
117 /* Size of not-last data sector. */
161 /* Support for NV-DDR2/3 work mode. */
163 /* Support for NV-DDR work mode. */
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H A Dmarvell_nand.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell NAND flash controller driver
6 * Author: Miquel RAYNAL <miquel.raynal@free-electrons.com>
9 * This NAND controller driver handles two versions of the hardware,
17 * The ECC layouts are depicted in details in Marvell AN-379, but here
28 * +-------------------------------------------------------------+
30 * +-------------------------------------------------------------+
39 * +-----------------------------------------
41 * +-----------------------------------------
43 * -------------------------------------------
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H A Darasan-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
114 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
124 * struct anfc_op - Defines how to execute an operation
150 * struct anand - Defines the NAND chip related information
151 * @node: Used to store NAND chips into a list
152 * @chip: NAND chip information structure
153 * @rb: Ready-busy line
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H A Dnand_base.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * This is the generic MTD driver for NAND flash devices. It should be
5 * capable of working with almost all NAND chips currently available.
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/nand-ecc-sw-hamming.h>
39 #include <linux/mtd/nand-ecc-sw-bch.h>
52 int lastpage = (mtd->erasesize / mtd->writesize) - 1; in nand_pairing_dist3_get_info()
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H A Dqcom_nandc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
18 #include <linux/mtd/nand-qpic-common.h>
21 * NAND special boot partitions
57 * NAND chip structure
62 * @chip: base NAND chip structure
82 * ecc/non-ecc mode for the current nand flash
132 ((u8 *)chip->controller - sizeof(struct qcom_nand_controller)); in get_qcom_nand_controller()
137 return ioread32(nandc->base + offset); in nandc_read()
143 iowrite32(val, nandc->base + offset); in nandc_write()
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/linux/include/linux/mtd/
H A Dnand.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2017 - Free Electrons
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
18 * struct nand_memory_organization - Memory organization structure
19 * @bits_per_cell: number of bits per NAND cell
27 * @ntargets: total number of targets exposed by the NAND device
55 * struct nand_row_converter - Information needed to convert an absolute offset
67 * struct nand_pos - NAND position object
68 * @target: the NAND target/die
74 * These information are usually used by specific sub-layers to select the
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H A Drawnand.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8 * Contains standard defines and IDs for NAND flash devices
17 #include <linux/mtd/nand.h>
29 /* The maximum number of NAND chips in an array */
50 * Standard NAND flash commands
75 #define NAND_CMD_NONE -1
84 #define NAND_DATA_IFACE_CHECK_ONLY -1
97 * Enable generic NAND 'page erased' check. This check is only done when
98 * ecc.correct() returns -EBADMSG.
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H A Dsh_flctl.h1 /* SPDX-License-Identifier: GPL-2.0
3 * SuperH FLCTL nand controller
18 #define FLCMNCR(f) (f->reg + 0x0)
19 #define FLCMDCR(f) (f->reg + 0x4)
20 #define FLCMCDR(f) (f->reg + 0x8)
21 #define FLADR(f) (f->reg + 0xC)
22 #define FLADR2(f) (f->reg + 0x3C)
23 #define FLDATAR(f) (f->reg + 0x10)
24 #define FLDTCNTR(f) (f->reg + 0x14)
25 #define FLINTDMACR(f) (f->reg + 0x18)
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H A Dplatnand.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
7 * Contains all platform NAND related definitions.
18 * struct platform_nand_chip - chip level device structure
26 * @part_probe_types: NULL-terminated array of probe types
40 * struct platform_nand_ctrl - controller level device structure
65 * struct platform_nand_data - container structure for platform-specific data
H A Dmtd.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> et al.
15 #include <linux/nvmem-provider.h>
17 #include <mtd/mtd-abi.h>
21 #define MTD_FAIL_ADDR_UNKNOWN -1LL
50 * struct mtd_oob_ops - oob operation operands
61 * @datbuf: data buffer - if NULL only oob data are read/written
65 * one go. If you try to do that on such an MTD device, -EINVAL will be
67 * devices you should split the write request into several sub-requests when the
83 * struct mtd_oob_region - oob region definition
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/linux/drivers/pinctrl/
H A Dpinctrl-xway.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/pinctrl/pinmux-xway.c
4 * based on linux/drivers/pinctrl/pinmux-pxa910.c
21 #include "pinctrl-lantiq.h"
110 /* --------- ase related code --------- */
238 /* --------- danube related code --------- */
341 GRP_MUX("nand ale", EBU, danube_pins_nand_ale),
342 GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1),
343 GRP_MUX("nand cle", EBU, danube_pins_nand_cle),
389 "nand ale", "nand cs1",
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/linux/fs/jffs2/
H A DREADME.Locking3 ---------------------------
11 ---------
13 The alloc_sem is a per-filesystem mutex, used primarily to ensure
24 which they belong. This is for the benefit of NAND flash - adding new
26 until this happens we ensure that any data in the write-buffer at the
28 was written afterwards. Hence, we can ensure the newly-obsoleted nodes
29 don't actually get erased until the write-buffer has been flushed to
32 With the introduction of NAND flash support and the write-buffer,
33 the alloc_sem is also used to protect the wbuf-related members of the
37 Ordering constraints: See f->sem.
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/linux/Documentation/devicetree/bindings/leds/
H A Dcommon.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
25 led-sources:
30 $ref: /schemas/types.yaml#/definitions/uint32-array
35 from the header include/dt-bindings/leds/common.h. If there is no
42 the header include/dt-bindings/leds/common.h. If there is no matching
48 function-enumerator:
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/linux/Documentation/networking/devlink/
H A Diosm.rst1 .. SPDX-License-Identifier: GPL-2.0
13 The ``iosm`` driver implements the following driver-specific parameters.
15 .. list-table:: Driver-specific parameters implemented
18 * - Name
19 - Type
20 - Mode
21 - Description
22 * - ``erase_full_flash``
23 - u8
24 - runtime
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/linux/include/linux/mfd/syscon/
H A Datmel-smc.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
26 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8)
34 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x10)
53 #define ATMEL_SMC_MODE_TDF(x) (((x) - 1) << 16)
65 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0xc)
80 * struct atmel_smc_cs_conf - SMC CS config as described in the datasheet.
84 * @timings: advanced NAND related timings (only applicable to HSMC)
/linux/arch/arm/mach-omap1/
H A Dboard-ams-delta.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/board-ams-delta.c
5 * Modified from board-generic.c
19 #include <linux/mtd/nand-gpio.h>
29 #include <linux/platform_data/gpio-omap.h>
30 #include <linux/soc/ti/omap1-mux.h>
33 #include <asm/mach-types.h>
37 #include <linux/platform_data/keypad-omap.h>
41 #include "ams-delta-fiq.h"
42 #include "board-ams-delta.h"
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/linux/drivers/memory/
H A Domap-gpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
33 #include <linux/omap-gpmc.h>
37 #include <linux/platform_data/mtd-nand-omap2.h>
39 #define DEVICE_NAME "omap-gpmc"
191 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
258 /* Define chip-selects as reserved by default until probe completes */
306 * gpmc_get_clk_period - get period of selected clock domain in ps
343 return (time_ns * 1000 + tick_ps - 1) / tick_ps; in gpmc_ns_to_clk_ticks()
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/linux/Documentation/leds/
H A Dleds-class.rst8 of the LED (taking a value 0-max_brightness). Most LEDs don't have hardware
9 brightness support so will just be turned on for non-zero brightness settings.
14 existing subsystems with minimal additional code. Examples are the disk-activity,
15 nand-disk and sharpsl-charge triggers. With led triggers disabled, the code
48 - devicename:
51 than to the hardware; the information related to the product and the bus
57 - color:
59 include/dt-bindings/leds/common.h.
61 - function:
63 include/dt-bindings/leds/common.h.
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/linux/drivers/media/platform/marvell/
H A Dcafe-driver.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Copyright 2006-11 One Laptop Per Child Association, Inc.
11 * Copyright 2006-11 Jonathan Corbet <corbet@lwn.net>
28 #include <media/v4l2-device.h>
36 #include "mcam-core.h"
57 * Most of the camera controller registers are defined in mcam-core.h,
82 #define TWSIC0_MODE 0x00000002 /* 1 = 16-bit, 0 = 8-bit */
127 * Debugging and related.
130 dev_err(&(cam)->pdev->dev, fmt, ##arg);
132 dev_warn(&(cam)->pdev->dev, fmt, ##arg);
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/linux/drivers/pinctrl/bcm/
H A Dpinctrl-cygnus-mux.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014-2017 Broadcom
20 #include <linux/pinctrl/pinconf-generic.h>
26 #include "../pinctrl-utils.h"
135 * @gpio_mux: GPIO override related information
548 CYGNUS_PIN_GROUP(nand, 0x14, 20, 0),
685 CYGNUS_PIN_FUNCTION(nand),
702 return pinctrl->num_groups; in cygnus_get_groups_count()
710 return pinctrl->groups[selector].name; in cygnus_get_group_name()
719 *pins = pinctrl->groups[selector].pins; in cygnus_get_group_pins()
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