Lines Matching +full:nand +full:- +full:related
1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence NAND flash controller driver
12 #include <linux/dma-mapping.h>
26 * - PIO - can work in master or slave DMA
27 * - CDMA - needs Master DMA for accessing command descriptors.
28 * - Generic mode - can use only slave DMA.
31 * on NAND flash memory. Driver uses CDMA mode for
117 /* Size of not-last data sector. */
161 /* Support for NV-DDR2/3 work mode. */
163 /* Support for NV-DDR work mode. */
174 /* BCH Engine identification register 0 - correction strengths. */
181 /* BCH Engine identification register 1 - correction strengths. */
188 /* BCH Engine identification register 2 - sector sizes. */
202 /* 16 bit device connected to the NAND Flash interface. */
244 /* Register controlling DQ related timing. */
246 /* Register controlling DSQ related timing. */
252 /* Register controlling the gate and loopback control related timing. */
294 /* Generic command address sequence - address fields. */
296 /* Generic command address sequence - address size. */
306 /* ECC enabled flag of generic command data sequence - ECC enabled. */
308 /* Generic command data sequence - sector size. */
310 /* Generic command data sequence - sector count. */
312 /* Generic command data sequence - last sector size. */
334 * Command DMA descriptor flags - the next descriptor
344 /* Command descriptor status - operation fail. */
346 /* Command descriptor status - page erased. */
348 /* Command descriptor status - timeout occurred. */
355 /* Command descriptor status - uncorrectable ECC error. */
357 /* Command descriptor status - descriptor error. */
360 /* Status of operation - OK. */
362 /* Status of operation - FAIL. */
364 /* Status of operation - uncorrectable ECC error. */
366 /* Status of operation - page erased. */
368 /* Status of operation - correctable ECC error. */
370 /* Status of operation - unsuspected state. */
372 /* Status of operation - operation is not completed yet. */
394 /* Flash address is a 32-bit address comprising of BANK and ROW ADDR. */
435 /* Cadence NAND flash controller capabilities get from driver data. */
437 /* Skew value of the output signals of the NAND Flash interface. */
443 /* Cadence NAND flash controller capabilities read from registers. */
517 * part of oob area of NAND flash memory page.
522 /* Sector size. There are few sectors per mtd->writesize */
552 u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; in cadence_nand_dma_buf_ok()
566 ret = readl_relaxed_poll_timeout(cdns_ctrl->reg + reg_offset, in cadence_nand_wait_for_value()
571 dev_err(cdns_ctrl->dev, in cadence_nand_wait_for_value()
587 return -ETIMEDOUT; in cadence_nand_set_ecc_enable()
589 reg = readl_relaxed(cdns_ctrl->reg + ECC_CONFIG_0); in cadence_nand_set_ecc_enable()
596 writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0); in cadence_nand_set_ecc_enable()
606 if (cdns_ctrl->curr_corr_str_idx == corr_str_idx) in cadence_nand_set_ecc_strength()
609 reg = readl_relaxed(cdns_ctrl->reg + ECC_CONFIG_0); in cadence_nand_set_ecc_strength()
612 writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0); in cadence_nand_set_ecc_strength()
614 cdns_ctrl->curr_corr_str_idx = corr_str_idx; in cadence_nand_set_ecc_strength()
620 int i, corr_str_idx = -1; in cadence_nand_get_ecc_strength_idx()
623 if (cdns_ctrl->ecc_strengths[i] == strength) { in cadence_nand_get_ecc_strength_idx()
640 return -ETIMEDOUT; in cadence_nand_set_skip_marker_val()
642 reg = readl_relaxed(cdns_ctrl->reg + SKIP_BYTES_CONF); in cadence_nand_set_skip_marker_val()
647 writel_relaxed(reg, cdns_ctrl->reg + SKIP_BYTES_CONF); in cadence_nand_set_skip_marker_val()
662 return -ETIMEDOUT; in cadence_nand_set_skip_bytes_conf()
669 reg = readl_relaxed(cdns_ctrl->reg + SKIP_BYTES_CONF); in cadence_nand_set_skip_bytes_conf()
676 writel_relaxed(reg, cdns_ctrl->reg + SKIP_BYTES_CONF); in cadence_nand_set_skip_bytes_conf()
677 writel_relaxed(skip_bytes_offset, cdns_ctrl->reg + SKIP_BYTES_OFFSET); in cadence_nand_set_skip_bytes_conf()
689 reg = readl_relaxed(cdns_ctrl->reg + ECC_CONFIG_0); in cadence_nand_set_erase_detection()
696 writel_relaxed(reg, cdns_ctrl->reg + ECC_CONFIG_0); in cadence_nand_set_erase_detection()
697 writel_relaxed(bitflips_threshold, cdns_ctrl->reg + ECC_CONFIG_1); in cadence_nand_set_erase_detection()
708 return -ETIMEDOUT; in cadence_nand_set_access_width16()
710 reg = readl_relaxed(cdns_ctrl->reg + COMMON_SET); in cadence_nand_set_access_width16()
716 writel_relaxed(reg, cdns_ctrl->reg + COMMON_SET); in cadence_nand_set_access_width16()
725 writel_relaxed(irq_status->status, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_clear_interrupt()
726 writel_relaxed(irq_status->trd_status, in cadence_nand_clear_interrupt()
727 cdns_ctrl->reg + TRD_COMP_INT_STATUS); in cadence_nand_clear_interrupt()
728 writel_relaxed(irq_status->trd_error, in cadence_nand_clear_interrupt()
729 cdns_ctrl->reg + TRD_ERR_INT_STATUS); in cadence_nand_clear_interrupt()
736 irq_status->status = readl_relaxed(cdns_ctrl->reg + INTR_STATUS); in cadence_nand_read_int_status()
737 irq_status->trd_status = readl_relaxed(cdns_ctrl->reg in cadence_nand_read_int_status()
739 irq_status->trd_error = readl_relaxed(cdns_ctrl->reg in cadence_nand_read_int_status()
748 return irq_status->status || irq_status->trd_status || in irq_detected()
749 irq_status->trd_error; in irq_detected()
756 spin_lock_irqsave(&cdns_ctrl->irq_lock, flags); in cadence_nand_reset_irq()
757 memset(&cdns_ctrl->irq_status, 0, sizeof(cdns_ctrl->irq_status)); in cadence_nand_reset_irq()
758 memset(&cdns_ctrl->irq_mask, 0, sizeof(cdns_ctrl->irq_mask)); in cadence_nand_reset_irq()
759 spin_unlock_irqrestore(&cdns_ctrl->irq_lock, flags); in cadence_nand_reset_irq()
772 spin_lock(&cdns_ctrl->irq_lock); in cadence_nand_isr()
779 cdns_ctrl->irq_status.status |= irq_status.status; in cadence_nand_isr()
780 cdns_ctrl->irq_status.trd_status |= irq_status.trd_status; in cadence_nand_isr()
781 cdns_ctrl->irq_status.trd_error |= irq_status.trd_error; in cadence_nand_isr()
783 complete(&cdns_ctrl->complete); in cadence_nand_isr()
787 spin_unlock(&cdns_ctrl->irq_lock); in cadence_nand_isr()
795 writel_relaxed(INTR_ENABLE_INTR_EN | irq_mask->status, in cadence_nand_set_irq_mask()
796 cdns_ctrl->reg + INTR_ENABLE); in cadence_nand_set_irq_mask()
798 writel_relaxed(irq_mask->trd_error, in cadence_nand_set_irq_mask()
799 cdns_ctrl->reg + TRD_ERR_INT_STATUS_EN); in cadence_nand_set_irq_mask()
810 time_left = wait_for_completion_timeout(&cdns_ctrl->complete, in cadence_nand_wait_for_irq()
813 *irq_status = cdns_ctrl->irq_status; in cadence_nand_wait_for_irq()
816 dev_err(cdns_ctrl->dev, "timeout occurred:\n"); in cadence_nand_wait_for_irq()
817 dev_err(cdns_ctrl->dev, "\tstatus = 0x%x, mask = 0x%x\n", in cadence_nand_wait_for_irq()
818 irq_status->status, irq_mask->status); in cadence_nand_wait_for_irq()
819 dev_err(cdns_ctrl->dev, in cadence_nand_wait_for_irq()
821 irq_status->trd_status, irq_mask->trd_status); in cadence_nand_wait_for_irq()
822 dev_err(cdns_ctrl->dev, in cadence_nand_wait_for_irq()
824 irq_status->trd_error, irq_mask->trd_error); in cadence_nand_wait_for_irq()
828 /* Execute generic command on NAND controller. */
842 return -ETIMEDOUT; in cadence_nand_generic_cmd_send()
846 writel_relaxed(mini_ctrl_cmd_l, cdns_ctrl->reg + CMD_REG2); in cadence_nand_generic_cmd_send()
847 writel_relaxed(mini_ctrl_cmd_h, cdns_ctrl->reg + CMD_REG3); in cadence_nand_generic_cmd_send()
855 writel_relaxed(reg, cdns_ctrl->reg + CMD_REG0); in cadence_nand_generic_cmd_send()
876 dev_err(cdns_ctrl->dev, "Timeout while waiting for SDMA\n"); in cadence_nand_wait_on_sdma()
877 return -ETIMEDOUT; in cadence_nand_wait_on_sdma()
881 *out_sdma_size = readl_relaxed(cdns_ctrl->reg + SDMA_SIZE); in cadence_nand_wait_on_sdma()
882 *out_sdma_trd = readl_relaxed(cdns_ctrl->reg + SDMA_TRD_NUM); in cadence_nand_wait_on_sdma()
886 dev_err(cdns_ctrl->dev, "SDMA error - irq_status %x\n", in cadence_nand_wait_on_sdma()
888 return -EIO; in cadence_nand_wait_on_sdma()
898 reg = readl_relaxed(cdns_ctrl->reg + CTRL_FEATURES); in cadence_nand_get_caps()
900 cdns_ctrl->caps2.max_banks = 1 << FIELD_GET(CTRL_FEATURES_N_BANKS, reg); in cadence_nand_get_caps()
903 cdns_ctrl->caps2.data_dma_width = 8; in cadence_nand_get_caps()
905 cdns_ctrl->caps2.data_dma_width = 4; in cadence_nand_get_caps()
908 cdns_ctrl->caps2.data_control_supp = true; in cadence_nand_get_caps()
912 cdns_ctrl->caps2.is_phy_type_dll = true; in cadence_nand_get_caps()
921 struct cadence_nand_cdma_desc *cdma_desc = cdns_ctrl->cdma_desc; in cadence_nand_cdma_desc_prepare()
926 cdma_desc->flash_pointer = flash_ptr; in cadence_nand_cdma_desc_prepare()
927 if (cdns_ctrl->ctrl_rev >= 13) in cadence_nand_cdma_desc_prepare()
928 cdma_desc->bank = nf_mem; in cadence_nand_cdma_desc_prepare()
930 cdma_desc->flash_pointer |= (nf_mem << CDMA_CFPTR_MEM_SHIFT); in cadence_nand_cdma_desc_prepare()
932 cdma_desc->command_flags |= CDMA_CF_DMA_MASTER; in cadence_nand_cdma_desc_prepare()
933 cdma_desc->command_flags |= CDMA_CF_INT; in cadence_nand_cdma_desc_prepare()
935 cdma_desc->memory_pointer = mem_ptr; in cadence_nand_cdma_desc_prepare()
936 cdma_desc->status = 0; in cadence_nand_cdma_desc_prepare()
937 cdma_desc->sync_flag_pointer = 0; in cadence_nand_cdma_desc_prepare()
938 cdma_desc->sync_arguments = 0; in cadence_nand_cdma_desc_prepare()
940 cdma_desc->command_type = ctype; in cadence_nand_cdma_desc_prepare()
941 cdma_desc->ctrl_data_ptr = ctrl_data_ptr; in cadence_nand_cdma_desc_prepare()
954 dev_err(cdns_ctrl->dev, ":CDMA desc error flag detected.\n"); in cadence_nand_check_desc_error()
966 struct cadence_nand_cdma_desc *desc_ptr = cdns_ctrl->cdma_desc; in cadence_nand_cdma_finish()
969 if (desc_ptr->status & CDMA_CS_FAIL) { in cadence_nand_cdma_finish()
971 desc_ptr->status); in cadence_nand_cdma_finish()
972 dev_err(cdns_ctrl->dev, ":CDMA error %x\n", desc_ptr->status); in cadence_nand_cdma_finish()
973 } else if (desc_ptr->status & CDMA_CS_COMP) { in cadence_nand_cdma_finish()
975 if (desc_ptr->command_flags & CDMA_CF_CONT) { in cadence_nand_cdma_finish()
976 dev_info(cdns_ctrl->dev, "DMA unsupported flag is set"); in cadence_nand_cdma_finish()
1001 reinit_completion(&cdns_ctrl->complete); in cadence_nand_cdma_send()
1003 writel_relaxed((u32)cdns_ctrl->dma_cdma_desc, in cadence_nand_cdma_send()
1004 cdns_ctrl->reg + CMD_REG2); in cadence_nand_cdma_send()
1005 writel_relaxed(0, cdns_ctrl->reg + CMD_REG3); in cadence_nand_cdma_send()
1012 writel_relaxed(reg, cdns_ctrl->reg + CMD_REG0); in cadence_nand_cdma_send()
1039 dev_err(cdns_ctrl->dev, "CDMA command timeout\n"); in cadence_nand_cdma_send_and_wait()
1040 return -ETIMEDOUT; in cadence_nand_cdma_send_and_wait()
1043 dev_err(cdns_ctrl->dev, "CDMA command failed\n"); in cadence_nand_cdma_send_and_wait()
1044 return -EIO; in cadence_nand_cdma_send_and_wait()
1078 struct nand_ecc_caps *ecc_caps = &cdns_ctrl->ecc_caps; in cadence_nand_read_bch_caps()
1082 reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_3); in cadence_nand_read_bch_caps()
1083 cdns_ctrl->bch_metadata_size = FIELD_GET(BCH_CFG_3_METADATA_SIZE, reg); in cadence_nand_read_bch_caps()
1084 if (cdns_ctrl->bch_metadata_size < 4) { in cadence_nand_read_bch_caps()
1085 dev_err(cdns_ctrl->dev, in cadence_nand_read_bch_caps()
1087 return -EIO; in cadence_nand_read_bch_caps()
1090 reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_0); in cadence_nand_read_bch_caps()
1091 cdns_ctrl->ecc_strengths[0] = FIELD_GET(BCH_CFG_0_CORR_CAP_0, reg); in cadence_nand_read_bch_caps()
1092 cdns_ctrl->ecc_strengths[1] = FIELD_GET(BCH_CFG_0_CORR_CAP_1, reg); in cadence_nand_read_bch_caps()
1093 cdns_ctrl->ecc_strengths[2] = FIELD_GET(BCH_CFG_0_CORR_CAP_2, reg); in cadence_nand_read_bch_caps()
1094 cdns_ctrl->ecc_strengths[3] = FIELD_GET(BCH_CFG_0_CORR_CAP_3, reg); in cadence_nand_read_bch_caps()
1096 reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_1); in cadence_nand_read_bch_caps()
1097 cdns_ctrl->ecc_strengths[4] = FIELD_GET(BCH_CFG_1_CORR_CAP_4, reg); in cadence_nand_read_bch_caps()
1098 cdns_ctrl->ecc_strengths[5] = FIELD_GET(BCH_CFG_1_CORR_CAP_5, reg); in cadence_nand_read_bch_caps()
1099 cdns_ctrl->ecc_strengths[6] = FIELD_GET(BCH_CFG_1_CORR_CAP_6, reg); in cadence_nand_read_bch_caps()
1100 cdns_ctrl->ecc_strengths[7] = FIELD_GET(BCH_CFG_1_CORR_CAP_7, reg); in cadence_nand_read_bch_caps()
1102 reg = readl_relaxed(cdns_ctrl->reg + BCH_CFG_2); in cadence_nand_read_bch_caps()
1103 cdns_ctrl->ecc_stepinfos[0].stepsize = in cadence_nand_read_bch_caps()
1106 cdns_ctrl->ecc_stepinfos[1].stepsize = in cadence_nand_read_bch_caps()
1111 if (cdns_ctrl->ecc_strengths[i] != 0) in cadence_nand_read_bch_caps()
1115 ecc_caps->nstepinfos = 0; in cadence_nand_read_bch_caps()
1118 cdns_ctrl->ecc_stepinfos[i].nstrengths = nstrengths; in cadence_nand_read_bch_caps()
1119 cdns_ctrl->ecc_stepinfos[i].strengths = in cadence_nand_read_bch_caps()
1120 cdns_ctrl->ecc_strengths; in cadence_nand_read_bch_caps()
1122 if (cdns_ctrl->ecc_stepinfos[i].stepsize != 0) in cadence_nand_read_bch_caps()
1123 ecc_caps->nstepinfos++; in cadence_nand_read_bch_caps()
1125 if (cdns_ctrl->ecc_stepinfos[i].stepsize > max_step_size) in cadence_nand_read_bch_caps()
1126 max_step_size = cdns_ctrl->ecc_stepinfos[i].stepsize; in cadence_nand_read_bch_caps()
1128 ecc_caps->stepinfos = &cdns_ctrl->ecc_stepinfos[0]; in cadence_nand_read_bch_caps()
1132 ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_256; in cadence_nand_read_bch_caps()
1135 ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_512; in cadence_nand_read_bch_caps()
1138 ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_1024; in cadence_nand_read_bch_caps()
1141 ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_2048; in cadence_nand_read_bch_caps()
1144 ecc_caps->calc_ecc_bytes = &cadence_nand_calc_ecc_bytes_4096; in cadence_nand_read_bch_caps()
1147 dev_err(cdns_ctrl->dev, in cadence_nand_read_bch_caps()
1150 return -EIO; in cadence_nand_read_bch_caps()
1168 reg = readl_relaxed(cdns_ctrl->reg + CTRL_VERSION); in cadence_nand_hw_init()
1169 cdns_ctrl->ctrl_rev = FIELD_GET(CTRL_VERSION_REV, reg); in cadence_nand_hw_init()
1171 dev_info(cdns_ctrl->dev, in cadence_nand_hw_init()
1172 "%s: cadence nand controller version reg %x\n", in cadence_nand_hw_init()
1176 writel_relaxed(0, cdns_ctrl->reg + MULTIPLANE_CFG); in cadence_nand_hw_init()
1177 writel_relaxed(0, cdns_ctrl->reg + CACHE_CFG); in cadence_nand_hw_init()
1180 writel_relaxed(0xFFFFFFFF, cdns_ctrl->reg + INTR_STATUS); in cadence_nand_hw_init()
1184 return -EIO; in cadence_nand_hw_init()
1187 if (cdns_ctrl->caps2.data_dma_width == 8) { in cadence_nand_hw_init()
1188 dev_err(cdns_ctrl->dev, in cadence_nand_hw_init()
1189 "cannot access 64-bit dma on !64-bit architectures"); in cadence_nand_hw_init()
1190 return -EIO; in cadence_nand_hw_init()
1214 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_prepare_data_size()
1218 u32 last_sec_size = cdns_chip->sector_size; in cadence_nand_prepare_data_size()
1222 if (cdns_ctrl->curr_trans_type == transfer_type) in cadence_nand_prepare_data_size()
1227 sec_cnt = cdns_chip->sector_count; in cadence_nand_prepare_data_size()
1228 sec_size = cdns_chip->sector_size; in cadence_nand_prepare_data_size()
1229 data_ctrl_size = cdns_chip->avail_oob_size; in cadence_nand_prepare_data_size()
1232 sec_cnt = cdns_chip->sector_count; in cadence_nand_prepare_data_size()
1233 last_sec_size = cdns_chip->sector_size in cadence_nand_prepare_data_size()
1234 + cdns_chip->avail_oob_size; in cadence_nand_prepare_data_size()
1235 sec_size = cdns_chip->sector_size; in cadence_nand_prepare_data_size()
1238 last_sec_size = mtd->writesize + mtd->oobsize; in cadence_nand_prepare_data_size()
1241 offset = mtd->writesize + cdns_chip->bbm_offs; in cadence_nand_prepare_data_size()
1249 writel_relaxed(reg, cdns_ctrl->reg + TRAN_CFG_0); in cadence_nand_prepare_data_size()
1254 writel_relaxed(reg, cdns_ctrl->reg + TRAN_CFG_1); in cadence_nand_prepare_data_size()
1256 if (cdns_ctrl->caps2.data_control_supp) { in cadence_nand_prepare_data_size()
1257 reg = readl_relaxed(cdns_ctrl->reg + CONTROL_DATA_CTRL); in cadence_nand_prepare_data_size()
1260 writel_relaxed(reg, cdns_ctrl->reg + CONTROL_DATA_CTRL); in cadence_nand_prepare_data_size()
1263 cdns_ctrl->curr_trans_type = transfer_type; in cadence_nand_prepare_data_size()
1284 dma_buf = dma_map_single(cdns_ctrl->dev, buf, buf_size, dir); in cadence_nand_cdma_transfer()
1285 if (dma_mapping_error(cdns_ctrl->dev, dma_buf)) { in cadence_nand_cdma_transfer()
1286 dev_err(cdns_ctrl->dev, "Failed to map DMA buffer\n"); in cadence_nand_cdma_transfer()
1287 return -EIO; in cadence_nand_cdma_transfer()
1291 dma_ctrl_dat = dma_map_single(cdns_ctrl->dev, ctrl_dat, in cadence_nand_cdma_transfer()
1293 if (dma_mapping_error(cdns_ctrl->dev, dma_ctrl_dat)) { in cadence_nand_cdma_transfer()
1294 dma_unmap_single(cdns_ctrl->dev, dma_buf, in cadence_nand_cdma_transfer()
1296 dev_err(cdns_ctrl->dev, "Failed to map DMA buffer\n"); in cadence_nand_cdma_transfer()
1297 return -EIO; in cadence_nand_cdma_transfer()
1306 dma_unmap_single(cdns_ctrl->dev, dma_buf, in cadence_nand_cdma_transfer()
1310 dma_unmap_single(cdns_ctrl->dev, dma_ctrl_dat, in cadence_nand_cdma_transfer()
1321 writel_relaxed(t->async_toggle_timings, in cadence_nand_set_timings()
1322 cdns_ctrl->reg + ASYNC_TOGGLE_TIMINGS); in cadence_nand_set_timings()
1323 writel_relaxed(t->timings0, cdns_ctrl->reg + TIMINGS0); in cadence_nand_set_timings()
1324 writel_relaxed(t->timings1, cdns_ctrl->reg + TIMINGS1); in cadence_nand_set_timings()
1325 writel_relaxed(t->timings2, cdns_ctrl->reg + TIMINGS2); in cadence_nand_set_timings()
1327 if (cdns_ctrl->caps2.is_phy_type_dll) in cadence_nand_set_timings()
1328 writel_relaxed(t->dll_phy_ctrl, cdns_ctrl->reg + DLL_PHY_CTRL); in cadence_nand_set_timings()
1330 writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL); in cadence_nand_set_timings()
1332 if (cdns_ctrl->caps2.is_phy_type_dll) { in cadence_nand_set_timings()
1333 writel_relaxed(0, cdns_ctrl->reg + PHY_TSEL); in cadence_nand_set_timings()
1334 writel_relaxed(2, cdns_ctrl->reg + PHY_DQ_TIMING); in cadence_nand_set_timings()
1335 writel_relaxed(t->phy_dqs_timing, in cadence_nand_set_timings()
1336 cdns_ctrl->reg + PHY_DQS_TIMING); in cadence_nand_set_timings()
1337 writel_relaxed(t->phy_gate_lpbk_ctrl, in cadence_nand_set_timings()
1338 cdns_ctrl->reg + PHY_GATE_LPBK_CTRL); in cadence_nand_set_timings()
1340 cdns_ctrl->reg + PHY_DLL_MASTER_CTRL); in cadence_nand_set_timings()
1341 writel_relaxed(0, cdns_ctrl->reg + PHY_DLL_SLAVE_CTRL); in cadence_nand_set_timings()
1347 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_select_target()
1350 if (chip == cdns_ctrl->selected_chip) in cadence_nand_select_target()
1356 return -ETIMEDOUT; in cadence_nand_select_target()
1358 cadence_nand_set_timings(cdns_ctrl, &cdns_chip->timings); in cadence_nand_select_target()
1361 cdns_chip->corr_str_idx); in cadence_nand_select_target()
1364 chip->ecc.strength); in cadence_nand_select_target()
1366 cdns_ctrl->curr_trans_type = -1; in cadence_nand_select_target()
1367 cdns_ctrl->selected_chip = chip; in cadence_nand_select_target()
1374 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_erase()
1377 u8 thread_nr = cdns_chip->cs[chip->cur_cs]; in cadence_nand_erase()
1380 cdns_chip->cs[chip->cur_cs], in cadence_nand_erase()
1385 dev_err(cdns_ctrl->dev, "erase operation failed\n"); in cadence_nand_erase()
1386 return -EIO; in cadence_nand_erase()
1399 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_read_bbm()
1412 cdns_chip->cs[chip->cur_cs], in cadence_nand_read_bbm()
1413 page, cdns_ctrl->buf, NULL, in cadence_nand_read_bbm()
1414 mtd->oobsize, in cadence_nand_read_bbm()
1417 dev_err(cdns_ctrl->dev, "read BBM failed\n"); in cadence_nand_read_bbm()
1418 return -EIO; in cadence_nand_read_bbm()
1421 memcpy(buf + cdns_chip->bbm_offs, cdns_ctrl->buf, cdns_chip->bbm_len); in cadence_nand_read_bbm()
1430 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_write_page()
1440 cadence_nand_set_skip_bytes_conf(cdns_ctrl, cdns_chip->bbm_len, in cadence_nand_write_page()
1441 mtd->writesize in cadence_nand_write_page()
1442 + cdns_chip->bbm_offs, in cadence_nand_write_page()
1446 marker_val = *(u16 *)(chip->oob_poi in cadence_nand_write_page()
1447 + cdns_chip->bbm_offs); in cadence_nand_write_page()
1450 memset(cdns_ctrl->buf + mtd->writesize, 0xFF, in cadence_nand_write_page()
1451 cdns_chip->avail_oob_size); in cadence_nand_write_page()
1458 if (cadence_nand_dma_buf_ok(cdns_ctrl, buf, mtd->writesize) && in cadence_nand_write_page()
1459 cdns_ctrl->caps2.data_control_supp) { in cadence_nand_write_page()
1463 oob = chip->oob_poi; in cadence_nand_write_page()
1465 oob = cdns_ctrl->buf + mtd->writesize; in cadence_nand_write_page()
1468 cdns_chip->cs[chip->cur_cs], in cadence_nand_write_page()
1470 mtd->writesize, in cadence_nand_write_page()
1471 cdns_chip->avail_oob_size, in cadence_nand_write_page()
1474 dev_err(cdns_ctrl->dev, "write page failed\n"); in cadence_nand_write_page()
1475 return -EIO; in cadence_nand_write_page()
1483 memcpy(cdns_ctrl->buf + mtd->writesize, chip->oob_poi, in cadence_nand_write_page()
1484 cdns_chip->avail_oob_size); in cadence_nand_write_page()
1487 memcpy(cdns_ctrl->buf, buf, mtd->writesize); in cadence_nand_write_page()
1492 cdns_chip->cs[chip->cur_cs], in cadence_nand_write_page()
1493 page, cdns_ctrl->buf, NULL, in cadence_nand_write_page()
1494 mtd->writesize in cadence_nand_write_page()
1495 + cdns_chip->avail_oob_size, in cadence_nand_write_page()
1501 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_write_oob()
1504 memset(cdns_ctrl->buf, 0xFF, mtd->writesize); in cadence_nand_write_oob()
1506 return cadence_nand_write_page(chip, cdns_ctrl->buf, 1, page); in cadence_nand_write_oob()
1513 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_write_page_raw()
1516 int writesize = mtd->writesize; in cadence_nand_write_page_raw()
1517 int oobsize = mtd->oobsize; in cadence_nand_write_page_raw()
1518 int ecc_steps = chip->ecc.steps; in cadence_nand_write_page_raw()
1519 int ecc_size = chip->ecc.size; in cadence_nand_write_page_raw()
1520 int ecc_bytes = chip->ecc.bytes; in cadence_nand_write_page_raw()
1521 void *tmp_buf = cdns_ctrl->buf; in cadence_nand_write_page_raw()
1522 int oob_skip = cdns_chip->bbm_len; in cadence_nand_write_page_raw()
1549 len = writesize - pos; in cadence_nand_write_page_raw()
1554 len = ecc_size - len; in cadence_nand_write_page_raw()
1563 const u8 *oob = chip->oob_poi; in cadence_nand_write_page_raw()
1564 u32 oob_data_offset = (cdns_chip->sector_count - 1) * in cadence_nand_write_page_raw()
1565 (cdns_chip->sector_size + chip->ecc.bytes) in cadence_nand_write_page_raw()
1566 + cdns_chip->sector_size + oob_skip; in cadence_nand_write_page_raw()
1573 cdns_chip->avail_oob_size); in cadence_nand_write_page_raw()
1574 oob += cdns_chip->avail_oob_size; in cadence_nand_write_page_raw()
1579 if (i == (ecc_steps - 1)) in cadence_nand_write_page_raw()
1580 pos += cdns_chip->avail_oob_size; in cadence_nand_write_page_raw()
1587 len = writesize - pos; in cadence_nand_write_page_raw()
1592 len = ecc_bytes - len; in cadence_nand_write_page_raw()
1603 cdns_chip->cs[chip->cur_cs], in cadence_nand_write_page_raw()
1604 page, cdns_ctrl->buf, NULL, in cadence_nand_write_page_raw()
1605 mtd->writesize + in cadence_nand_write_page_raw()
1606 mtd->oobsize, in cadence_nand_write_page_raw()
1619 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_read_page()
1629 cadence_nand_set_skip_bytes_conf(cdns_ctrl, cdns_chip->bbm_len, in cadence_nand_read_page()
1630 mtd->writesize in cadence_nand_read_page()
1631 + cdns_chip->bbm_offs, 1); in cadence_nand_read_page()
1637 if (cadence_nand_dma_buf_ok(cdns_ctrl, buf, mtd->writesize) && in cadence_nand_read_page()
1638 cdns_ctrl->caps2.data_control_supp) { in cadence_nand_read_page()
1642 oob = chip->oob_poi; in cadence_nand_read_page()
1644 oob = cdns_ctrl->buf + mtd->writesize; in cadence_nand_read_page()
1648 cdns_chip->cs[chip->cur_cs], in cadence_nand_read_page()
1650 mtd->writesize, in cadence_nand_read_page()
1651 cdns_chip->avail_oob_size, in cadence_nand_read_page()
1657 cdns_chip->cs[chip->cur_cs], in cadence_nand_read_page()
1658 page, cdns_ctrl->buf, in cadence_nand_read_page()
1659 NULL, mtd->writesize in cadence_nand_read_page()
1660 + cdns_chip->avail_oob_size, in cadence_nand_read_page()
1663 memcpy(buf, cdns_ctrl->buf, mtd->writesize); in cadence_nand_read_page()
1665 memcpy(chip->oob_poi, in cadence_nand_read_page()
1666 cdns_ctrl->buf + mtd->writesize, in cadence_nand_read_page()
1667 mtd->oobsize); in cadence_nand_read_page()
1672 mtd->ecc_stats.failed++; in cadence_nand_read_page()
1677 cdns_ctrl->cdma_desc->status); in cadence_nand_read_page()
1678 mtd->ecc_stats.corrected += ecc_err_count; in cadence_nand_read_page()
1684 dev_err(cdns_ctrl->dev, "read page failed\n"); in cadence_nand_read_page()
1685 return -EIO; in cadence_nand_read_page()
1689 if (cadence_nand_read_bbm(chip, page, chip->oob_poi)) in cadence_nand_read_page()
1690 return -EIO; in cadence_nand_read_page()
1698 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_read_oob()
1700 return cadence_nand_read_page(chip, cdns_ctrl->buf, 1, page); in cadence_nand_read_oob()
1706 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_read_page_raw()
1709 int oob_skip = cdns_chip->bbm_len; in cadence_nand_read_page_raw()
1710 int writesize = mtd->writesize; in cadence_nand_read_page_raw()
1711 int ecc_steps = chip->ecc.steps; in cadence_nand_read_page_raw()
1712 int ecc_size = chip->ecc.size; in cadence_nand_read_page_raw()
1713 int ecc_bytes = chip->ecc.bytes; in cadence_nand_read_page_raw()
1714 void *tmp_buf = cdns_ctrl->buf; in cadence_nand_read_page_raw()
1726 cdns_chip->cs[chip->cur_cs], in cadence_nand_read_page_raw()
1727 page, cdns_ctrl->buf, NULL, in cadence_nand_read_page_raw()
1728 mtd->writesize in cadence_nand_read_page_raw()
1729 + mtd->oobsize, in cadence_nand_read_page_raw()
1737 dev_err(cdns_ctrl->dev, "read raw page failed\n"); in cadence_nand_read_page_raw()
1738 return -EIO; in cadence_nand_read_page_raw()
1750 len = writesize - pos; in cadence_nand_read_page_raw()
1755 len = ecc_size - len; in cadence_nand_read_page_raw()
1764 u8 *oob = chip->oob_poi; in cadence_nand_read_page_raw()
1765 u32 oob_data_offset = (cdns_chip->sector_count - 1) * in cadence_nand_read_page_raw()
1766 (cdns_chip->sector_size + chip->ecc.bytes) in cadence_nand_read_page_raw()
1767 + cdns_chip->sector_size + oob_skip; in cadence_nand_read_page_raw()
1771 cdns_chip->avail_oob_size); in cadence_nand_read_page_raw()
1776 oob += cdns_chip->avail_oob_size; in cadence_nand_read_page_raw()
1783 if (i == (ecc_steps - 1)) in cadence_nand_read_page_raw()
1784 pos += cdns_chip->avail_oob_size; in cadence_nand_read_page_raw()
1789 len = writesize - pos; in cadence_nand_read_page_raw()
1794 len = ecc_bytes - len; in cadence_nand_read_page_raw()
1830 chan = cdns_ctrl->dmac; in cadence_nand_slave_dma_transfer()
1831 dma_dev = chan->device; in cadence_nand_slave_dma_transfer()
1833 buf_dma = dma_map_single(dma_dev->dev, buf, len, dir); in cadence_nand_slave_dma_transfer()
1834 if (dma_mapping_error(dma_dev->dev, buf_dma)) { in cadence_nand_slave_dma_transfer()
1835 dev_err(cdns_ctrl->dev, "Failed to map DMA buffer\n"); in cadence_nand_slave_dma_transfer()
1840 src_dma = cdns_ctrl->io.iova_dma; in cadence_nand_slave_dma_transfer()
1844 dst_dma = cdns_ctrl->io.iova_dma; in cadence_nand_slave_dma_transfer()
1847 tx = dmaengine_prep_dma_memcpy(cdns_ctrl->dmac, dst_dma, src_dma, len, in cadence_nand_slave_dma_transfer()
1850 dev_err(cdns_ctrl->dev, "Failed to prepare DMA memcpy\n"); in cadence_nand_slave_dma_transfer()
1854 tx->callback = cadence_nand_slave_dma_transfer_finished; in cadence_nand_slave_dma_transfer()
1855 tx->callback_param = &finished; in cadence_nand_slave_dma_transfer()
1859 dev_err(cdns_ctrl->dev, "Failed to do DMA tx_submit\n"); in cadence_nand_slave_dma_transfer()
1863 dma_async_issue_pending(cdns_ctrl->dmac); in cadence_nand_slave_dma_transfer()
1866 dma_unmap_single(dma_dev->dev, buf_dma, len, dir); in cadence_nand_slave_dma_transfer()
1871 dma_unmap_single(dma_dev->dev, buf_dma, len, dir); in cadence_nand_slave_dma_transfer()
1874 dev_dbg(cdns_ctrl->dev, "Fall back to CPU I/O\n"); in cadence_nand_slave_dma_transfer()
1876 return -EIO; in cadence_nand_slave_dma_transfer()
1891 if (!cdns_ctrl->caps1->has_dma) { in cadence_nand_read_buf()
1892 u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; in cadence_nand_read_buf()
1898 ioread32_rep(cdns_ctrl->io.virt, buf, len_in_words); in cadence_nand_read_buf()
1901 readsq(cdns_ctrl->io.virt, buf, len_in_words); in cadence_nand_read_buf()
1910 ioread32_rep(cdns_ctrl->io.virt, in cadence_nand_read_buf()
1911 cdns_ctrl->buf, in cadence_nand_read_buf()
1912 sdma_size / 4 - len_in_words); in cadence_nand_read_buf()
1915 readsq(cdns_ctrl->io.virt, cdns_ctrl->buf, in cadence_nand_read_buf()
1916 sdma_size / 8 - len_in_words); in cadence_nand_read_buf()
1920 memcpy(buf + read_bytes, cdns_ctrl->buf, in cadence_nand_read_buf()
1921 len - read_bytes); in cadence_nand_read_buf()
1928 cdns_ctrl->io.dma, in cadence_nand_read_buf()
1933 dev_warn(cdns_ctrl->dev, in cadence_nand_read_buf()
1938 status = cadence_nand_slave_dma_transfer(cdns_ctrl, cdns_ctrl->buf, in cadence_nand_read_buf()
1939 cdns_ctrl->io.dma, in cadence_nand_read_buf()
1943 dev_err(cdns_ctrl->dev, "Slave DMA transfer failed"); in cadence_nand_read_buf()
1947 memcpy(buf, cdns_ctrl->buf, len); in cadence_nand_read_buf()
1964 if (!cdns_ctrl->caps1->has_dma) { in cadence_nand_write_buf()
1965 u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; in cadence_nand_write_buf()
1970 iowrite32_rep(cdns_ctrl->io.virt, buf, len_in_words); in cadence_nand_write_buf()
1973 writesq(cdns_ctrl->io.virt, buf, len_in_words); in cadence_nand_write_buf()
1981 memcpy(cdns_ctrl->buf, buf + written_bytes, in cadence_nand_write_buf()
1982 len - written_bytes); in cadence_nand_write_buf()
1984 /* write all expected by nand controller data */ in cadence_nand_write_buf()
1986 iowrite32_rep(cdns_ctrl->io.virt, in cadence_nand_write_buf()
1987 cdns_ctrl->buf, in cadence_nand_write_buf()
1988 sdma_size / 4 - len_in_words); in cadence_nand_write_buf()
1991 writesq(cdns_ctrl->io.virt, cdns_ctrl->buf, in cadence_nand_write_buf()
1992 sdma_size / 8 - len_in_words); in cadence_nand_write_buf()
2001 cdns_ctrl->io.dma, in cadence_nand_write_buf()
2006 dev_warn(cdns_ctrl->dev, in cadence_nand_write_buf()
2011 memcpy(cdns_ctrl->buf, buf, len); in cadence_nand_write_buf()
2013 status = cadence_nand_slave_dma_transfer(cdns_ctrl, cdns_ctrl->buf, in cadence_nand_write_buf()
2014 cdns_ctrl->io.dma, in cadence_nand_write_buf()
2018 dev_err(cdns_ctrl->dev, "Slave DMA transfer failed"); in cadence_nand_write_buf()
2026 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_force_byte_access()
2029 * Callers of this function do not verify if the NAND is using a 16-bit in cadence_nand_force_byte_access()
2030 * an 8-bit bus for normal operations, so we need to take care of that in cadence_nand_force_byte_access()
2031 * here by leaving the configuration unchanged if the NAND does not have in cadence_nand_force_byte_access()
2034 if (!(chip->options & NAND_BUSWIDTH_16)) in cadence_nand_force_byte_access()
2043 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_cmd_opcode()
2050 instr = &subop->instrs[op_id]; in cadence_nand_cmd_opcode()
2052 if (instr->delay_ns > 0) in cadence_nand_cmd_opcode()
2058 instr->ctx.cmd.opcode); in cadence_nand_cmd_opcode()
2061 cdns_chip->cs[chip->cur_cs], in cadence_nand_cmd_opcode()
2064 dev_err(cdns_ctrl->dev, "send cmd %x failed\n", in cadence_nand_cmd_opcode()
2065 instr->ctx.cmd.opcode); in cadence_nand_cmd_opcode()
2073 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_cmd_address()
2084 instr = &subop->instrs[op_id]; in cadence_nand_cmd_address()
2086 if (instr->delay_ns > 0) in cadence_nand_cmd_address()
2094 addrs = &instr->ctx.addr.addrs[offset]; in cadence_nand_cmd_address()
2102 naddrs - 1); in cadence_nand_cmd_address()
2105 cdns_chip->cs[chip->cur_cs], in cadence_nand_cmd_address()
2108 dev_err(cdns_ctrl->dev, "send address %llx failed\n", address); in cadence_nand_cmd_address()
2118 if (subop->instrs[0].ctx.cmd.opcode == NAND_CMD_ERASE1) { in cadence_nand_cmd_erase()
2125 instr = &subop->instrs[1]; in cadence_nand_cmd_erase()
2128 addrs = &instr->ctx.addr.addrs[offset]; in cadence_nand_cmd_erase()
2140 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in cadence_nand_cmd_erase()
2143 .cs = chip->cur_cs, in cadence_nand_cmd_erase()
2144 .instrs = &subop->instrs[op_id], in cadence_nand_cmd_erase()
2146 ret = chip->controller->ops->exec_op(chip, &nand_op, false); in cadence_nand_cmd_erase()
2157 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_cmd_data()
2165 instr = &subop->instrs[op_id]; in cadence_nand_cmd_data()
2167 if (instr->delay_ns > 0) in cadence_nand_cmd_data()
2173 if (instr->type == NAND_OP_DATA_OUT_INSTR) in cadence_nand_cmd_data()
2181 if (instr->ctx.data.force_8bit) { in cadence_nand_cmd_data()
2184 dev_err(cdns_ctrl->dev, in cadence_nand_cmd_data()
2191 cdns_chip->cs[chip->cur_cs], in cadence_nand_cmd_data()
2194 dev_err(cdns_ctrl->dev, "send generic data cmd failed\n"); in cadence_nand_cmd_data()
2198 if (instr->type == NAND_OP_DATA_IN_INSTR) { in cadence_nand_cmd_data()
2199 void *buf = instr->ctx.data.buf.in + offset; in cadence_nand_cmd_data()
2203 const void *buf = instr->ctx.data.buf.out + offset; in cadence_nand_cmd_data()
2209 dev_err(cdns_ctrl->dev, "data transfer failed for generic command\n"); in cadence_nand_cmd_data()
2213 if (instr->ctx.data.force_8bit) { in cadence_nand_cmd_data()
2216 dev_err(cdns_ctrl->dev, in cadence_nand_cmd_data()
2229 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_cmd_waitrdy()
2231 const struct nand_op_instr *instr = &subop->instrs[op_id]; in cadence_nand_cmd_waitrdy()
2232 u32 timeout_us = instr->ctx.waitrdy.timeout_ms * 1000; in cadence_nand_cmd_waitrdy()
2236 BIT(cdns_chip->cs[chip->cur_cs]), in cadence_nand_cmd_waitrdy()
2287 return -ERANGE; in cadence_nand_ooblayout_free()
2289 oobregion->offset = cdns_chip->bbm_len; in cadence_nand_ooblayout_free()
2290 oobregion->length = cdns_chip->avail_oob_size in cadence_nand_ooblayout_free()
2291 - cdns_chip->bbm_len; in cadence_nand_ooblayout_free()
2303 return -ERANGE; in cadence_nand_ooblayout_ecc()
2305 oobregion->offset = cdns_chip->avail_oob_size; in cadence_nand_ooblayout_ecc()
2306 oobregion->length = chip->ecc.total; in cadence_nand_ooblayout_ecc()
2324 return timing / clock - 1; in calc_cycl()
2345 return (trp_cnt + 1) * clk_period + trhoh_min - trea_max; in calc_tdvw()
2353 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_setup_interface()
2355 struct cadence_nand_timings *t = &cdns_chip->timings; in cadence_nand_setup_interface()
2357 u32 board_delay = cdns_ctrl->board_delay; in cadence_nand_setup_interface()
2359 cdns_ctrl->nf_clk_rate); in cadence_nand_setup_interface()
2364 u32 if_skew = cdns_ctrl->caps1->if_skew; in cadence_nand_setup_interface()
2365 u32 board_delay_skew_min = board_delay - if_skew; in cadence_nand_setup_interface()
2380 if (cdns_ctrl->caps2.is_phy_type_dll) in cadence_nand_setup_interface()
2387 tdvw_min = sdr->tREA_max + board_delay_skew_max; in cadence_nand_setup_interface()
2397 if (sdr->tRC_min <= clk_period && in cadence_nand_setup_interface()
2398 sdr->tRP_min <= (clk_period / 2) && in cadence_nand_setup_interface()
2399 sdr->tREH_min <= (clk_period / 2)) { in cadence_nand_setup_interface()
2402 tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min, in cadence_nand_setup_interface()
2403 sdr->tREA_max, ext_rd_mode); in cadence_nand_setup_interface()
2404 tdvw_max = calc_tdvw_max(trp_cnt, clk_period, sdr->tRHOH_min, in cadence_nand_setup_interface()
2427 trp_cnt = (sdr->tREA_max + board_delay_skew_max in cadence_nand_setup_interface()
2437 trp_cnt = calc_cycl(sdr->tRP_min, clk_period); in cadence_nand_setup_interface()
2438 trh = sdr->tRC_min - ((trp_cnt + 1) * clk_period); in cadence_nand_setup_interface()
2439 if (sdr->tREH_min >= trh) in cadence_nand_setup_interface()
2440 trh_cnt = calc_cycl(sdr->tREH_min, clk_period); in cadence_nand_setup_interface()
2444 tdvw = calc_tdvw(trp_cnt, clk_period, sdr->tRHOH_min, in cadence_nand_setup_interface()
2445 sdr->tREA_max, ext_rd_mode); in cadence_nand_setup_interface()
2449 * - if not extend the tRP timings. in cadence_nand_setup_interface()
2453 sdr->tRHOH_min, in cadence_nand_setup_interface()
2460 (((tdvw_max / dqs_sampl_res - 1) in cadence_nand_setup_interface()
2477 trp_cnt = (sdr->tREA_max + board_delay_skew_max in cadence_nand_setup_interface()
2483 sdr->tRHOH_min, in cadence_nand_setup_interface()
2486 if (sdr->tWC_min <= clk_period && in cadence_nand_setup_interface()
2487 (sdr->tWP_min + if_skew) <= (clk_period / 2) && in cadence_nand_setup_interface()
2488 (sdr->tWH_min + if_skew) <= (clk_period / 2)) { in cadence_nand_setup_interface()
2494 twp_cnt = calc_cycl(sdr->tWP_min + if_skew, clk_period); in cadence_nand_setup_interface()
2495 if ((twp_cnt + 1) * clk_period < (sdr->tALS_min + if_skew)) in cadence_nand_setup_interface()
2496 twp_cnt = calc_cycl(sdr->tALS_min + if_skew, in cadence_nand_setup_interface()
2499 twh = (sdr->tWC_min - (twp_cnt + 1) * clk_period); in cadence_nand_setup_interface()
2500 if (sdr->tWH_min >= twh) in cadence_nand_setup_interface()
2501 twh = sdr->tWH_min; in cadence_nand_setup_interface()
2510 t->async_toggle_timings = reg; in cadence_nand_setup_interface()
2511 dev_dbg(cdns_ctrl->dev, "ASYNC_TOGGLE_TIMINGS_SDR\t%x\n", reg); in cadence_nand_setup_interface()
2513 tadl_cnt = calc_cycl((sdr->tADL_min + if_skew), clk_period); in cadence_nand_setup_interface()
2514 tccs_cnt = calc_cycl((sdr->tCCS_min + if_skew), clk_period); in cadence_nand_setup_interface()
2515 twhr_cnt = calc_cycl((sdr->tWHR_min + if_skew), clk_period); in cadence_nand_setup_interface()
2516 trhw_cnt = calc_cycl((sdr->tRHW_min + if_skew), clk_period); in cadence_nand_setup_interface()
2530 t->timings0 = reg; in cadence_nand_setup_interface()
2531 dev_dbg(cdns_ctrl->dev, "TIMINGS0_SDR\t%x\n", reg); in cadence_nand_setup_interface()
2533 /* The following is related to single signal so skew is not needed. */ in cadence_nand_setup_interface()
2534 trhz_cnt = calc_cycl(sdr->tRHZ_max, clk_period); in cadence_nand_setup_interface()
2536 twb_cnt = calc_cycl((sdr->tWB_max + board_delay), clk_period); in cadence_nand_setup_interface()
2539 * first value is related with sync, second value is related in cadence_nand_setup_interface()
2544 * The following is related to the we edge of the random data input in cadence_nand_setup_interface()
2551 t->timings1 = reg; in cadence_nand_setup_interface()
2552 dev_dbg(cdns_ctrl->dev, "TIMINGS1_SDR\t%x\n", reg); in cadence_nand_setup_interface()
2554 tfeat_cnt = calc_cycl(sdr->tFEAT_max, clk_period); in cadence_nand_setup_interface()
2558 tceh_cnt = calc_cycl(sdr->tCEH_min, clk_period); in cadence_nand_setup_interface()
2559 tcs_cnt = calc_cycl((sdr->tCS_min + if_skew), clk_period); in cadence_nand_setup_interface()
2564 t->timings2 = reg; in cadence_nand_setup_interface()
2565 dev_dbg(cdns_ctrl->dev, "TIMINGS2_SDR\t%x\n", reg); in cadence_nand_setup_interface()
2567 if (cdns_ctrl->caps2.is_phy_type_dll) { in cadence_nand_setup_interface()
2576 t->dll_phy_ctrl = reg; in cadence_nand_setup_interface()
2577 dev_dbg(cdns_ctrl->dev, "DLL_PHY_CTRL_SDR\t%x\n", reg); in cadence_nand_setup_interface()
2584 sampling_point = (tdvw_max / dqs_sampl_res - 1); in cadence_nand_setup_interface()
2600 / phony_dqs_mod - 1; in cadence_nand_setup_interface()
2602 if (!cdns_ctrl->caps2.is_phy_type_dll) in cadence_nand_setup_interface()
2603 phony_dqs_timing--; in cadence_nand_setup_interface()
2606 phony_dqs_timing--; in cadence_nand_setup_interface()
2610 dev_warn(cdns_ctrl->dev, in cadence_nand_setup_interface()
2615 if (cdns_ctrl->caps2.is_phy_type_dll) in cadence_nand_setup_interface()
2617 t->phy_ctrl = reg; in cadence_nand_setup_interface()
2618 dev_dbg(cdns_ctrl->dev, "PHY_CTRL_REG_SDR\t%x\n", reg); in cadence_nand_setup_interface()
2620 if (cdns_ctrl->caps2.is_phy_type_dll) { in cadence_nand_setup_interface()
2621 dev_dbg(cdns_ctrl->dev, "PHY_TSEL_REG_SDR\t%x\n", 0); in cadence_nand_setup_interface()
2622 dev_dbg(cdns_ctrl->dev, "PHY_DQ_TIMING_REG_SDR\t%x\n", 2); in cadence_nand_setup_interface()
2623 dev_dbg(cdns_ctrl->dev, "PHY_DQS_TIMING_REG_SDR\t%x\n", in cadence_nand_setup_interface()
2625 t->phy_dqs_timing = dll_phy_dqs_timing; in cadence_nand_setup_interface()
2628 dev_dbg(cdns_ctrl->dev, "PHY_GATE_LPBK_CTRL_REG_SDR\t%x\n", in cadence_nand_setup_interface()
2630 t->phy_gate_lpbk_ctrl = reg; in cadence_nand_setup_interface()
2632 dev_dbg(cdns_ctrl->dev, "PHY_DLL_MASTER_CTRL_REG_SDR\t%lx\n", in cadence_nand_setup_interface()
2634 dev_dbg(cdns_ctrl->dev, "PHY_DLL_SLAVE_CTRL_REG_SDR\t%x\n", 0); in cadence_nand_setup_interface()
2642 struct cdns_nand_ctrl *cdns_ctrl = to_cdns_nand_ctrl(chip->controller); in cadence_nand_attach_chip()
2648 if (chip->options & NAND_BUSWIDTH_16) { in cadence_nand_attach_chip()
2654 chip->bbt_options |= NAND_BBT_USE_FLASH; in cadence_nand_attach_chip()
2655 chip->bbt_options |= NAND_BBT_NO_OOB; in cadence_nand_attach_chip()
2656 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in cadence_nand_attach_chip()
2658 chip->options |= NAND_NO_SUBPAGE_WRITE; in cadence_nand_attach_chip()
2660 cdns_chip->bbm_offs = chip->badblockpos; in cadence_nand_attach_chip()
2661 cdns_chip->bbm_offs &= ~0x01; in cadence_nand_attach_chip()
2663 cdns_chip->bbm_len = 2; in cadence_nand_attach_chip()
2666 &cdns_ctrl->ecc_caps, in cadence_nand_attach_chip()
2667 mtd->oobsize - cdns_chip->bbm_len); in cadence_nand_attach_chip()
2669 dev_err(cdns_ctrl->dev, "ECC configuration failed\n"); in cadence_nand_attach_chip()
2673 dev_dbg(cdns_ctrl->dev, in cadence_nand_attach_chip()
2675 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes); in cadence_nand_attach_chip()
2678 cdns_chip->sector_size = chip->ecc.size; in cadence_nand_attach_chip()
2679 cdns_chip->sector_count = mtd->writesize / cdns_chip->sector_size; in cadence_nand_attach_chip()
2680 ecc_size = cdns_chip->sector_count * chip->ecc.bytes; in cadence_nand_attach_chip()
2682 cdns_chip->avail_oob_size = mtd->oobsize - ecc_size; in cadence_nand_attach_chip()
2684 if (cdns_chip->avail_oob_size > cdns_ctrl->bch_metadata_size) in cadence_nand_attach_chip()
2685 cdns_chip->avail_oob_size = cdns_ctrl->bch_metadata_size; in cadence_nand_attach_chip()
2687 if ((cdns_chip->avail_oob_size + cdns_chip->bbm_len + ecc_size) in cadence_nand_attach_chip()
2688 > mtd->oobsize) in cadence_nand_attach_chip()
2689 cdns_chip->avail_oob_size -= 4; in cadence_nand_attach_chip()
2691 ret = cadence_nand_get_ecc_strength_idx(cdns_ctrl, chip->ecc.strength); in cadence_nand_attach_chip()
2693 return -EINVAL; in cadence_nand_attach_chip()
2695 cdns_chip->corr_str_idx = (u8)ret; in cadence_nand_attach_chip()
2700 return -ETIMEDOUT; in cadence_nand_attach_chip()
2703 cdns_chip->corr_str_idx); in cadence_nand_attach_chip()
2706 chip->ecc.strength); in cadence_nand_attach_chip()
2709 chip->ecc.read_page = cadence_nand_read_page; in cadence_nand_attach_chip()
2710 chip->ecc.read_page_raw = cadence_nand_read_page_raw; in cadence_nand_attach_chip()
2711 chip->ecc.write_page = cadence_nand_write_page; in cadence_nand_attach_chip()
2712 chip->ecc.write_page_raw = cadence_nand_write_page_raw; in cadence_nand_attach_chip()
2713 chip->ecc.read_oob = cadence_nand_read_oob; in cadence_nand_attach_chip()
2714 chip->ecc.write_oob = cadence_nand_write_oob; in cadence_nand_attach_chip()
2715 chip->ecc.read_oob_raw = cadence_nand_read_oob_raw; in cadence_nand_attach_chip()
2716 chip->ecc.write_oob_raw = cadence_nand_write_oob_raw; in cadence_nand_attach_chip()
2718 if ((mtd->writesize + mtd->oobsize) > cdns_ctrl->buf_size) in cadence_nand_attach_chip()
2719 cdns_ctrl->buf_size = mtd->writesize + mtd->oobsize; in cadence_nand_attach_chip()
2721 /* Is 32-bit DMA supported? */ in cadence_nand_attach_chip()
2722 ret = dma_set_mask(cdns_ctrl->dev, DMA_BIT_MASK(32)); in cadence_nand_attach_chip()
2724 dev_err(cdns_ctrl->dev, "no usable DMA configuration\n"); in cadence_nand_attach_chip()
2750 dev_err(cdns_ctrl->dev, "missing/invalid reg property\n"); in cadence_nand_chip_init()
2751 return -EINVAL; in cadence_nand_chip_init()
2754 /* Allocate the nand chip structure. */ in cadence_nand_chip_init()
2755 cdns_chip = devm_kzalloc(cdns_ctrl->dev, sizeof(*cdns_chip) + in cadence_nand_chip_init()
2759 dev_err(cdns_ctrl->dev, "could not allocate chip structure\n"); in cadence_nand_chip_init()
2760 return -ENOMEM; in cadence_nand_chip_init()
2763 cdns_chip->nsels = nsels; in cadence_nand_chip_init()
2769 dev_err(cdns_ctrl->dev, in cadence_nand_chip_init()
2775 if (cs >= cdns_ctrl->caps2.max_banks) { in cadence_nand_chip_init()
2776 dev_err(cdns_ctrl->dev, in cadence_nand_chip_init()
2778 cs, cdns_ctrl->caps2.max_banks); in cadence_nand_chip_init()
2779 return -EINVAL; in cadence_nand_chip_init()
2782 if (test_and_set_bit(cs, &cdns_ctrl->assigned_cs)) { in cadence_nand_chip_init()
2783 dev_err(cdns_ctrl->dev, in cadence_nand_chip_init()
2785 return -EINVAL; in cadence_nand_chip_init()
2788 cdns_chip->cs[i] = cs; in cadence_nand_chip_init()
2791 chip = &cdns_chip->chip; in cadence_nand_chip_init()
2792 chip->controller = &cdns_ctrl->controller; in cadence_nand_chip_init()
2796 mtd->dev.parent = cdns_ctrl->dev; in cadence_nand_chip_init()
2799 * Default to HW ECC engine mode. If the nand-ecc-mode property is given in cadence_nand_chip_init()
2802 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in cadence_nand_chip_init()
2804 ret = nand_scan(chip, cdns_chip->nsels); in cadence_nand_chip_init()
2806 dev_err(cdns_ctrl->dev, "could not scan the nand chip\n"); in cadence_nand_chip_init()
2812 dev_err(cdns_ctrl->dev, in cadence_nand_chip_init()
2818 list_add_tail(&cdns_chip->node, &cdns_ctrl->chips); in cadence_nand_chip_init()
2829 list_for_each_entry_safe(entry, temp, &cdns_ctrl->chips, node) { in cadence_nand_chips_cleanup()
2830 chip = &entry->chip; in cadence_nand_chips_cleanup()
2834 list_del(&entry->node); in cadence_nand_chips_cleanup()
2840 struct device_node *np = cdns_ctrl->dev->of_node; in cadence_nand_chips_init()
2841 int max_cs = cdns_ctrl->caps2.max_banks; in cadence_nand_chips_init()
2847 dev_err(cdns_ctrl->dev, in cadence_nand_chips_init()
2848 "too many NAND chips: %d (max = %d CS)\n", in cadence_nand_chips_init()
2850 return -EINVAL; in cadence_nand_chips_init()
2868 writel_relaxed(INTR_ENABLE_INTR_EN, cdns_ctrl->reg + INTR_ENABLE); in cadence_nand_irq_cleanup()
2874 struct dma_device *dma_dev = cdns_ctrl->dmac->device; in cadence_nand_init()
2877 cdns_ctrl->cdma_desc = dma_alloc_coherent(cdns_ctrl->dev, in cadence_nand_init()
2878 sizeof(*cdns_ctrl->cdma_desc), in cadence_nand_init()
2879 &cdns_ctrl->dma_cdma_desc, in cadence_nand_init()
2881 if (!cdns_ctrl->dma_cdma_desc) in cadence_nand_init()
2882 return -ENOMEM; in cadence_nand_init()
2884 cdns_ctrl->buf_size = SZ_16K; in cadence_nand_init()
2885 cdns_ctrl->buf = kmalloc(cdns_ctrl->buf_size, GFP_KERNEL); in cadence_nand_init()
2886 if (!cdns_ctrl->buf) { in cadence_nand_init()
2887 ret = -ENOMEM; in cadence_nand_init()
2891 if (devm_request_irq(cdns_ctrl->dev, cdns_ctrl->irq, cadence_nand_isr, in cadence_nand_init()
2892 IRQF_SHARED, "cadence-nand-controller", in cadence_nand_init()
2894 dev_err(cdns_ctrl->dev, "Unable to allocate IRQ\n"); in cadence_nand_init()
2895 ret = -ENODEV; in cadence_nand_init()
2899 spin_lock_init(&cdns_ctrl->irq_lock); in cadence_nand_init()
2900 init_completion(&cdns_ctrl->complete); in cadence_nand_init()
2909 if (cdns_ctrl->caps1->has_dma) { in cadence_nand_init()
2910 cdns_ctrl->dmac = dma_request_chan_by_mask(&mask); in cadence_nand_init()
2911 if (IS_ERR(cdns_ctrl->dmac)) { in cadence_nand_init()
2912 ret = dev_err_probe(cdns_ctrl->dev, PTR_ERR(cdns_ctrl->dmac), in cadence_nand_init()
2918 cdns_ctrl->io.iova_dma = dma_map_resource(dma_dev->dev, cdns_ctrl->io.dma, in cadence_nand_init()
2919 cdns_ctrl->io.size, in cadence_nand_init()
2922 ret = dma_mapping_error(dma_dev->dev, cdns_ctrl->io.iova_dma); in cadence_nand_init()
2924 dev_err(cdns_ctrl->dev, "Failed to map I/O resource to DMA\n"); in cadence_nand_init()
2928 nand_controller_init(&cdns_ctrl->controller); in cadence_nand_init()
2929 INIT_LIST_HEAD(&cdns_ctrl->chips); in cadence_nand_init()
2931 cdns_ctrl->controller.ops = &cadence_nand_controller_ops; in cadence_nand_init()
2932 cdns_ctrl->curr_corr_str_idx = 0xFF; in cadence_nand_init()
2936 dev_err(cdns_ctrl->dev, "Failed to register MTD: %d\n", in cadence_nand_init()
2941 kfree(cdns_ctrl->buf); in cadence_nand_init()
2942 cdns_ctrl->buf = kzalloc(cdns_ctrl->buf_size, GFP_KERNEL); in cadence_nand_init()
2943 if (!cdns_ctrl->buf) { in cadence_nand_init()
2944 ret = -ENOMEM; in cadence_nand_init()
2951 dma_unmap_resource(dma_dev->dev, cdns_ctrl->io.iova_dma, in cadence_nand_init()
2952 cdns_ctrl->io.size, DMA_BIDIRECTIONAL, 0); in cadence_nand_init()
2955 if (cdns_ctrl->dmac) in cadence_nand_init()
2956 dma_release_channel(cdns_ctrl->dmac); in cadence_nand_init()
2959 cadence_nand_irq_cleanup(cdns_ctrl->irq, cdns_ctrl); in cadence_nand_init()
2962 kfree(cdns_ctrl->buf); in cadence_nand_init()
2965 dma_free_coherent(cdns_ctrl->dev, sizeof(struct cadence_nand_cdma_desc), in cadence_nand_init()
2966 cdns_ctrl->cdma_desc, cdns_ctrl->dma_cdma_desc); in cadence_nand_init()
2975 if (cdns_ctrl->dmac) in cadence_nand_remove()
2976 dma_unmap_resource(cdns_ctrl->dmac->device->dev, in cadence_nand_remove()
2977 cdns_ctrl->io.iova_dma, cdns_ctrl->io.size, in cadence_nand_remove()
2979 cadence_nand_irq_cleanup(cdns_ctrl->irq, cdns_ctrl); in cadence_nand_remove()
2980 kfree(cdns_ctrl->buf); in cadence_nand_remove()
2981 dma_free_coherent(cdns_ctrl->dev, sizeof(struct cadence_nand_cdma_desc), in cadence_nand_remove()
2982 cdns_ctrl->cdma_desc, cdns_ctrl->dma_cdma_desc); in cadence_nand_remove()
2984 if (cdns_ctrl->dmac) in cadence_nand_remove()
2985 dma_release_channel(cdns_ctrl->dmac); in cadence_nand_remove()
3000 .compatible = "cdns,hp-nfc",
3016 devdata = device_get_match_data(&ofdev->dev); in cadence_nand_dt_probe()
3019 return -ENOMEM; in cadence_nand_dt_probe()
3022 dt = devm_kzalloc(&ofdev->dev, sizeof(*dt), GFP_KERNEL); in cadence_nand_dt_probe()
3024 return -ENOMEM; in cadence_nand_dt_probe()
3026 cdns_ctrl = &dt->cdns_ctrl; in cadence_nand_dt_probe()
3027 cdns_ctrl->caps1 = devdata; in cadence_nand_dt_probe()
3029 cdns_ctrl->dev = &ofdev->dev; in cadence_nand_dt_probe()
3030 cdns_ctrl->irq = platform_get_irq(ofdev, 0); in cadence_nand_dt_probe()
3031 if (cdns_ctrl->irq < 0) in cadence_nand_dt_probe()
3032 return cdns_ctrl->irq; in cadence_nand_dt_probe()
3034 dev_info(cdns_ctrl->dev, "IRQ: nr %d\n", cdns_ctrl->irq); in cadence_nand_dt_probe()
3036 cdns_ctrl->reg = devm_platform_ioremap_resource(ofdev, 0); in cadence_nand_dt_probe()
3037 if (IS_ERR(cdns_ctrl->reg)) in cadence_nand_dt_probe()
3038 return PTR_ERR(cdns_ctrl->reg); in cadence_nand_dt_probe()
3040 cdns_ctrl->io.virt = devm_platform_get_and_ioremap_resource(ofdev, 1, &res); in cadence_nand_dt_probe()
3041 if (IS_ERR(cdns_ctrl->io.virt)) in cadence_nand_dt_probe()
3042 return PTR_ERR(cdns_ctrl->io.virt); in cadence_nand_dt_probe()
3044 cdns_ctrl->io.dma = res->start; in cadence_nand_dt_probe()
3045 cdns_ctrl->io.size = resource_size(res); in cadence_nand_dt_probe()
3047 dt->clk = devm_clk_get(cdns_ctrl->dev, "nf_clk"); in cadence_nand_dt_probe()
3048 if (IS_ERR(dt->clk)) in cadence_nand_dt_probe()
3049 return PTR_ERR(dt->clk); in cadence_nand_dt_probe()
3051 cdns_ctrl->nf_clk_rate = clk_get_rate(dt->clk); in cadence_nand_dt_probe()
3053 ret = of_property_read_u32(ofdev->dev.of_node, in cadence_nand_dt_probe()
3054 "cdns,board-delay-ps", &val); in cadence_nand_dt_probe()
3057 dev_info(cdns_ctrl->dev, in cadence_nand_dt_probe()
3058 "missing cdns,board-delay-ps property, %d was set\n", in cadence_nand_dt_probe()
3061 cdns_ctrl->board_delay = val; in cadence_nand_dt_probe()
3075 cadence_nand_remove(&dt->cdns_ctrl); in cadence_nand_dt_remove()
3082 .name = "cadence-nand-controller",
3091 MODULE_DESCRIPTION("Driver for Cadence NAND flash controller");