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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
32 … 0x001d00UL //Access:R DataWidth:0x2 // Multi Field Register.
37 … 0x001d04UL //Access:RW DataWidth:0x2 // Multi Field Register.
38 … (0x1<<0) // This bit masks, when set, the Interrupt bit: P…
40 … (0x1<<1) // This bit masks, when set, the Interrupt bit: P…
42 … 0x001d08UL //Access:WR DataWidth:0x2 // Multi Field Register.
47 … 0x001d0cUL //Access:RC DataWidth:0x2 // Multi Field Register.
54 …Access:RW DataWidth:0x4 // DBMUX register. Bit mask for enabling dword (128bit line) / qword …
55 …ess:RW DataWidth:0x2 // DBMUX register. Circular dword (128bit line) / qword (256bit line) …
56 … DataWidth:0x4 // DBMUX register. Bit mask for forcing the valid signal per dword (128bit line…
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/freebsd/sys/contrib/device-tree/Bindings/
H A Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-ma
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/freebsd/contrib/ofed/opensm/include/complib/
H A Dcl_atomic.h2 * Copyright (c) 2004-2006 Voltaire, Inc. All rights reserved.
3 * Copyright (c) 2002-2005 Mellanox Technologies LTD. All rights reserved.
4 * Copyright (c) 1996-2003 Intel Corporation. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
61 * 32-bit signed integers in an atomic fashion.
68 * The cl_atomic_inc function atomically increments a 32-bit signed
77 * [in] Pointer to a 32-bit integer to increment.
87 * synchronization mechanisms in multi-threaded environments.
98 * The cl_atomic_dec function atomically decrements a 32-bit signed
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H A Dcl_debug.h3 * Copyright (c) 2002-2005 Mellanox Technologies LTD. All rights reserved.
4 * Copyright (c) 1996-2003 Intel Corporation. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
187 * The debug output macros reserve the upper bit of the debug level to
208 * debug level to control non-error debug output. Error messages are
209 * always displayed, regardless of the lower bit definition.
211 * When specifying the debug output desired for non-error messages
262 * set in CHK_LVL unless the most significant bit is set (indicating an
266 * In multi-processor environments where the current processor can be
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/freebsd/sys/dev/sound/pci/
H A Denvy24ht.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
30 /* -------------------------------------------------------------------- */
37 #define ENVY24HT_PCIR_MT 0x14 /* Multi-Track I/O Base Address */
45 #define ENVY24HT_CCS_IMASK_PMT 0x10 /* Professional Multi-track */
65 #define ENVY24HT_CCSM_SCFG_MPU 0x20 /* 0(not implemented)/1(1) MPU-401 UART */
66 #define ENVY24HT_CCSM_SCFG_ADC 0x0c /* 1-2 stereo ADC connected, S/PDIF receiver connected */
67 #define ENVY24HT_CCSM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */
69 #define ENVY24HT_CCS_ACL 0x05 /* AC-Link Configuration Register */
70 #define ENVY24HT_CCSM_ACL_MTC 0x80 /* Multi-track converter type: 0:AC'97 1:I2S */
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H A Denvy24.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
29 /* -------------------------------------------------------------------- */
40 #define PCIR_MT 0x1c /* Professional Multi-Track I/O Base Address */
48 #define PCIM_LAC_MPU401 0x0008 /* MPU-401 I/O enable */
60 #define PCIM_LCC_MPUBASE 0x0006 /* MPU-401 base 300h-330h */
68 #define PCIM_SCFG_MPU 0x20 /* 1(0)/2(1) MPU-401 UART(s) */
71 #define PCIM_SCFG_ADC 0x0c /* 1-4 stereo ADC connected */
72 #define PCIM_SCFG_DAC 0x03 /* 1-4 stereo DAC connected */
74 #define PCIR_ACL 0x61 /* AC-Link Configuration Register */
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/freebsd/sys/contrib/device-tree/Bindings/timer/
H A Dandestech,atcpit100-timer.txt2 ------------------------------------------------------------------
6 This timer is a set of compact multi-function timers, which can be
10 multi-function timer and provide the following usage scenarios:
11 One 32-bit timer
12 Two 16-bit timers
13 Four 8-bit timers
14 One 16-bit PWM
15 One 16-bit timer and one 8-bit PWM
16 Two 8-bit timer and one 8-bit PWM
19 - compatible : Should be "andestech,atcpit100"
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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dmulti-inno,mi0283qt.txt1 Multi-Inno MI0283QT display panel
4 - compatible: "multi-inno,mi0283qt".
7 all mandatory properties described in ../spi/spi-bus.txt must be specified.
10 - dc-gpios: D/C pin. The presence/absence of this GPIO determines
12 - present: IM=x110 4-wire 8-bit data serial interface
13 - absent: IM=x101 3-wire 9-bit data serial interface
14 - reset-gpios: Reset pin
15 - power-supply: A regulator node for the supply voltage.
16 - backlight: phandle of the backlight device attached to the panel
17 - rotation: panel rotation in degrees counter clockwise (0,90,180,270)
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/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Dmac.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022, 2024 Intel Corporation
11 * AUX indices follows - 1 for non-CDB, 2 for CDB.
31 * enum iwl_mac_protection_flags - MA
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dusb251xb.txt1 Microchip USB 2.0 Hi-Speed Hub Controller
4 Hi-Speed Controller.
7 - compatible : Should be "microchip,usb251xb" or one of the specific types:
11 - reg : I2C address on the selected bus (default is <0x2C>)
14 - reset-gpios : Should specify the gpio for hub reset
15 - vdd-supply : Should specify the phandle to the regulator supplying vdd
16 - skip-config : Skip Hub configuration, but only send the USB-Attach command
17 - vendor-id : Set USB Vendor ID of the hub (16 bit, default is 0x0424)
18 - product-id : Set USB Product ID of the hub (16 bit, default depends on type)
19 - device-id : Set USB Device ID of the hub (16 bit, default is 0x0bb3)
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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dsnps,dma-spear1340.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
21 - enum:
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/freebsd/lib/libsys/
H A Duuidgen.247 See below for a more in-depth description of the identifiers.
51 According to the algorithm of generating time-based UUIDs, this will also
63 (GUIDs), have a binary representation of 128-bits.
66 .Bd -literal
76 .Bl -tag -width ".Va clock_seq_hi_and_reserved"
78 The least significant 32 bits of a 60-bit timestamp.
79 This field is stored in the native byte-order.
81 The least significant 16 bits of the most significant 28 bits of the 60-bit
83 This field is stored in the native byte-order.
85 The most significant 12 bits of the 60-bit timestamp multiplexed with a 4-bit
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/freebsd/contrib/wpa/src/common/
H A Dieee802_11_defs.h3 * Copyright (c) 2002-2019, Jouni Malinen <j@w1.fi>
4 * Copyright (c) 2007-2008 Intel Corporation
39 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
41 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
105 #define WLAN_CAPABILITY_ESS BIT(0)
106 #define WLAN_CAPABILITY_IBSS BIT(1)
107 #define WLAN_CAPABILITY_CF_POLLABLE BIT(2)
108 #define WLAN_CAPABILITY_CF_POLL_REQUEST BIT(3)
109 #define WLAN_CAPABILITY_PRIVACY BIT(4)
110 #define WLAN_CAPABILITY_SHORT_PREAMBLE BIT(5)
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/freebsd/share/man/man4/
H A Dng_ppp.41 .\" Copyright (c) 1996-1999 Whistle Communications, Inc.
19 .\" MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
51 user-land daemon).
54 user-land implementations.
56 multi-link PPP, Van Jacobson compression, PPP compression, PPP
58 A single PPP node corresponds to one PPP multi-link bundle.
71 Typically this node is connected to a user-land daemon via a
94 These device-independent hooks transmit and receive full PPP
96 information fields, but no checksum or other link-specific fields.
187 Only bundle-level compression and encryption is directly supported;
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H A Dsmp.429 .Nd description of the FreeBSD Symmetric Multi-Processor kernel
35 kernel implements symmetric multi-processor support.
43 the read-only sysctl variable
46 The number of online threads per CPU core is available in the read-only sysctl
50 read-only sysctl variable
54 allows specific CPUs on a multi-processor system to be disabled.
70 algorithms to make better use of modern multi-core CPUs.
77 by being cores in a single multi-core processor.
79 nesting level of the CPU group and "cache-level", corresponding to the
85 each bit position set to 1 signifies a CPU belonging to the group.
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H A Diicbus.441 system provides a uniform, modular and architecture-independent
49 easy way to connect a CPU to peripheral chips in a TV-set.
71 As mentioned before, the IC bus is a Multi-MASTER BUS.
77 .Bl -column "Device drivers" -compact
89 8-bit characters they write to the bus according to the I2C protocol.
92 bidirectional communications, thanks to the multi-master capabilities of the
97 .Bl -column "Interface drivers" -compact
100 .It Sy iicbb Ta "generic bit-banging master-only driver"
101 .It Sy lpbb Ta "parallel port specific bit-banging interface"
133 .Va clock-frequency
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
18 bit lines from the automatic calibrated position.
19 Two set of 3-tuple setting for each (up to 3)
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/freebsd/contrib/bearssl/inc/
H A Dbearssl_hash.h48 * - `br_xxx_vtable`
52 * - `br_xxx_SIZE`
57 * - `br_xxx_ID`
64 * standard](https://tools.ietf.org/html/rfc5246#section-7.4.1.4.1),
66 * 1 to 6 for MD5, SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512,
69 * - `br_xxx_context`
80 * - `br_xxx_init(br_xxx_context *ctx)`
88 * - `br_xxx_update(br_xxx_context *ctx, const void *data, size_t len)`
93 * - `br_xxx_out(const br_xxx_context *ctx, void *out)`
101 * - `br_xxx_state(const br_xxx_context *ctx, void *out)`
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/freebsd/lib/libpmc/pmu-events/arch/x86/amdzen1/
H A Dfloating-point.json5 "BriefDescription": "Total number multi-pipe uOps assigned to all pipes.",
6 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
12 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 3.",
13 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
19 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 2.",
20 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
26 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 1.",
27 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
33 "BriefDescription": "Total number multi-pipe uOps assigned to pipe 0.",
34 …-pipe uOps dispatched to each of the 4 FPU execution pipelines. This event reflects how busy the F…
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/freebsd/sys/contrib/device-tree/Bindings/powerpc/nintendo/
H A Dgamecube.txt7 This node represents the multi-function "Flipper" chip, which packages
12 - compatible : Should be "nintendo,flipper"
21 - compatible : should be "nintendo,flipper-vi"
22 - reg : should contain the VI registers location and length
23 - interrupts : should contain the VI interrupt
32 - compatible : should be "nintendo,flipper-pi"
33 - re
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines all of the AARCH64-specific intrinsics.
11 //===----------------------------------------------------------------------===//
61 //===----------------------------------------------------------------------===//
79 //===----------------------------------------------------------------------===//
89 // A space-consuming intrinsic primarily for testing block and jump table
95 //===----------------------------------------------------------------------===//
103 // the side-effect of updating gcspr, but this combination doesn't work
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/freebsd/contrib/tcsh/
H A Dconfig_f.h2 * config_f.h -- configure various defines for tcsh
9 /*-
45 * SHORT_STRINGS Use at least 16 bit characters instead of 8 bit chars
54 * Allows proper function in multibyte encodings like UTF-8
109 * KANJI Ignore meta-next, and the ISO character set. Should
116 * DSPMBYTE add variable "dspmbyte" and display multi-byte string at
125 * MBYTEDEBUG when "dspmbyte" is changed, set multi-byte checktable to
127 * (use for multi-byte table check)
163 * COLOR_LS_F Do you want to use builtin color ls-F ?
/freebsd/crypto/openssl/doc/man1/
H A Dopenssl-speed.pod.in2 {- OpenSSL::safe::output_do_not_edit_headers(); -}
6 openssl-speed - test library performance
11 [B<-help>]
12 [B<-elapsed>]
13 [B<-evp> I<algo>]
14 [B<-hmac> I<algo>]
15 [B<-cmac> I<algo>]
16 [B<-mb>]
17 [B<-aead>]
18 [B<-multi> I<num>]
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dsynopsys.txt1 Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
3 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
7 (16-bit) configuration.
9 These both ECC controllers correct single bit ECC errors and detect double bit
13 - compatible: One of:
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
16 - reg: Should contain DDR controller registers location and length.
18 Required properties for "xlnx,zynqmp-ddrc-2.40a":
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/freebsd/usr.bin/finger/
H A Dnet.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
58 int error, multi; in netfinger() local
80 multi = (ai0->ai_next) != 0; in netfinger()
83 if (ai0->ai_canonname == 0) in netfinger()
86 printf("[%s]\n", ai0->ai_canonname); in netfinger()
88 for (ai = ai0; ai != NULL; ai = ai->ai_next) { in netfinger()
89 if (multi) in netfinger()
111 s = socket(ai->ai_family, ai->ai_socktype, ai->ai_protocol); in do_protocol()
113 warn("socket(%d, %d, %d)", ai->ai_family, ai->ai_socktype, in do_protocol()
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