Lines Matching +full:multi +full:- +full:bit
1 //===- IntrinsicsAARCH64.td - Defines AARCH64 intrinsics ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines all of the AARCH64-specific intrinsics.
11 //===----------------------------------------------------------------------===//
61 //===----------------------------------------------------------------------===//
79 //===----------------------------------------------------------------------===//
89 // A space-consuming intrinsic primarily for testing block and jump table
95 //===----------------------------------------------------------------------===//
103 // the side-effect of updating gcspr, but this combination doesn't work
114 //===----------------------------------------------------------------------===//
278 // Vector Add High-Half
283 // Vector Rounding Add High-Half
307 // 64-bit polynomial multiply really returns an i128, which is not legal. Fake
330 // Vector Subtract High-Half
335 // Vector Rounding Subtract High-Half
338 // Vector Compare Absolute Greater-than-or-equal
341 // Vector Compare Absolute Greater-than
420 // Vector Signed->Unsigned Shift Left by Constant
423 // Vector Signed->Unsigned Narrowing Saturating Shift Right by Constant
426 // Vector Signed->Unsigned Rounding Narrowing Saturating Shift Right by Const
485 // Vector Conversions Between Half-Precision and Single-Precision.
491 // Vector Conversions Between Floating-point and Fixed-point.
497 // Vector FP->Int Conversions
509 // v8.5-A Vector FP Rounding
515 // Scalar FP->Int conversions
524 // v8.2-A Dot Product
528 // v8.6-A Matrix Multiply Intrinsics
542 // v8.6-A Bfloat Intrinsics
552 // v8.2-A FP16 Fused Multiply-Add Long
558 // v8.3-A Floating-point complex add
740 // Armv8.5-A Random number generation intrinsics
859 //===----------------------------------------------------------------------===//
882 //===----------------------------------------------------------------------===//
898 // The following are codegen-only intrinsics for stack instrumentation.
914 // ADDG ptr1, baseptr, (ptr0 - baseptr), tag_offset
928 // Update allocation tags for 16-aligned, 16-sized memory region, and store a pair 8-byte values.
933 //===----------------------------------------------------------------------===//
955 // Armv8.7-A load/store 64-byte intrinsics
1432 //===----------------------------------------------------------------------===//
1663 // Scalar + 32-bit scaled offset vector, zero extend, packed and
1670 // Scalar + 32-bit scaled offset vector, sign extend, packed and
1677 // Scalar + 64-bit scaled offset vector.
2029 // Floating-point arithmetic
2094 // Floating-point reductions
2111 // Floating-point conversions
2121 // Floating-point comparisons
2225 // 64 bit unscaled offsets
2228 // 64 bit scaled offsets
2231 // 32 bit unscaled offsets, sign (sxtw) or zero (zxtw) extended to 64 bits
2235 // 32 bit scaled offsets, sign (sxtw) or zero (zxtw) extended to 64 bits
2239 // 128-bit loads, scaled offsets (indices)
2242 // 128-bit loads, unscaled offsets
2251 // 128-bit loads, unscaled offsets
2255 // First-faulting gather loads: scalar base + vector offsets
2258 // 64 bit unscaled offsets
2261 // 64 bit scaled offsets
2264 // 32 bit unscaled offsets, sign (sxtw) or zero (uxtw) extended to 64 bits
2268 // 32 bit scaled offsets, sign (sxtw) or zero (uxtw) extended to 64 bits
2273 // First-faulting gather loads: vector base + scalar offset
2280 // Non-temporal gather loads: scalar base + vector offsets
2283 // 64 bit unscaled offsets
2286 // 64 bit indices
2289 // 32 bit unscaled offsets, zero (zxtw) extended to 64 bits
2293 // Non-temporal gather loads: vector base + scalar offset
2302 // 64 bit unscaled offsets
2305 // 64 bit scaled offsets
2309 // 32 bit unscaled offsets, sign (sxtw) or zero (zxtw) extended to 64 bits
2316 // 32 bit scaled offsets, sign (sxtw) or zero (zxtw) extended to 64 bits
2323 // 128-bit stores, scaled offsets (indices)
2326 // 128-bit stores, unscaled offsets
2335 // 128-bit stores, unscaled offsets
2339 // Non-temporal scatter stores: scalar base + vector offsets
2342 // 64 bit unscaled offsets
2345 // 64 bit indices
2349 // 32 bit unscaled offsets, zero (zxtw) extended to 64 bits
2353 // Non-temporal scatter stores: vector base + scalar offset
2359 // SVE2 - Uniform DSP operations
2411 // SVE2 - Widening DSP operations
2444 // SVE2 - Non-widening pairwise arithmetic
2459 // SVE2 - Widening pairwise arithmetic
2466 // SVE2 - Uniform complex integer arithmetic
2477 // SVE2 - Widening complex integer arithmetic
2485 // SVE2 - Widening complex integer dot product
2492 // SVE2 - Floating-point widening multiply-accumulate
2505 // SVE2 - Floating-point integer binary logarithm
2511 // SVE2 - Vector histogram count
2518 // SVE2 - Character match
2525 // SVE2 - Unary narrowing operations
2536 // SVE2 - Binary narrowing DSP operations
2557 // Saturating shift right - signed input/output
2564 // Saturating shift right - unsigned input/output
2571 // Saturating shift right - signed input, unsigned output
2628 // SVE2 - Polynomial arithmetic
2647 // SVE2 - Optional AES, SHA-3 and SM4
2679 // SVE2 - Extended table lookup/permute
2686 // SVE2 - Optional bit permutation
2725 // SVE2.1 - Contiguous loads to multiple consecutive vectors
2745 // SVE2.1 - Contiguous loads to quadword (single vector)
2756 // SVE2.1 - Contiguous store from quadword (single vector)
2776 // SVE2.1 - Contiguous stores to multiple consecutive vectors
2797 // SVE2 - Contiguous conflict detection
2990 // Predicate-pair intrinsics
2999 // Predicate-as-counter intrinsics
3034 // While (predicate-as-counter) intrinsics
3296 // Multi-vector fused multiply-add/subtract
3327 // Multi-vector rounding shift left intrinsics
3340 // Multi-vector saturating rounding shift right intrinsics
3359 // Multi-vector multiply-add/subtract long
3378 // Multi-vector multiply-add long long
3422 // Multi-vector zeroing
3428 // Multi-vector signed saturating doubling multiply high
3436 // Multi-vector floating-point round to integral value
3444 // Multi-vector min/max
3458 // Multi-vector floating point min/max number
3470 // Multi-vector vertical dot-products
3486 //Multi-vector floating-point convert from half-precision to deinterleaved single-precision.
3492 // Multi-vector floating-point CVT from single-precision to interleaved half-precision/BFloat16
3498 // Multi-vector convert to/from floating-point.
3512 // Multi-vector saturating extract narrow
3522 // Multi-vector saturating extract narrow and interleave
3532 // Multi-Single add/sub
3540 // Multi-Multi add/sub
3547 // Multi-vector clamps
3559 // Multi-vector add/sub and accumulate into ZA
3569 // Move multi-vectors to/from ZA
3591 // Multi-Single Vector add
3596 // 2-way and 4-way multi-vector signed/unsigned integer dot-product
3621 // Multi-vector half-precision or bfloat floating-point dot-product
3631 // Multi-vector zip and unzips
3641 // Vector dot-products (2-way)
3650 // Signed/unsigned multi-vector unpacks
3657 // 2-way and 4-way vector selects
3703 // SVE2.1 - ZIPQ1, ZIPQ2, UZPQ1, UZPQ2
3710 // SVE2.1 - Programmable table lookup within each quadword vector segment
3716 // SVE2.1 - Extract vector segment from each pair of quadword segments.
3721 // SVE2.1 - Move predicate to/from vector