Lines Matching +full:multi +full:- +full:bit

1 Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
3 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
7 (16-bit) configuration.
9 These both ECC controllers correct single bit ECC errors and detect double bit
13  - compatible: One of:
14 	- 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 	- 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
16  - reg: Should contain DDR controller registers location and length.
18 Required properties for "xlnx,zynqmp-ddrc-2.40a":
19  - interrupts: Property with a value describing the interrupt number.
22 	memory-controller@f8006000 {
23 		compatible = "xlnx,zynq-ddrc-a05";
27 	mc: memory-controller@fd070000 {
28 		compatible = "xlnx,zynqmp-ddrc-2.40a";
30 		interrupt-parent = <&gic>;