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/freebsd/sys/netinet/
H A Din_kdtrace.h58 SDT_PROVIDER_DECLARE(mib);
60 SDT_PROBE_DECLARE(mib, ip, count, ips_total);
61 SDT_PROBE_DECLARE(mib, ip, count, ips_badsum);
62 SDT_PROBE_DECLARE(mib, ip, count, ips_tooshort);
63 SDT_PROBE_DECLARE(mib, ip, count, ips_toosmall);
64 SDT_PROBE_DECLARE(mib, ip, count, ips_badhlen);
65 SDT_PROBE_DECLARE(mib, ip, count, ips_badlen);
66 SDT_PROBE_DECLARE(mib, ip, count, ips_fragments);
67 SDT_PROBE_DECLARE(mib, ip, count, ips_fragdropped);
68 SDT_PROBE_DECLARE(mib, ip, count, ips_fragtimeout);
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp75 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); in INITIALIZE_PASS() local
84 return TII->ExpandMOVI(MIB, MVT::i8); in INITIALIZE_PASS()
86 return TII->ExpandMOVI(MIB, MVT::i16); in INITIALIZE_PASS()
88 return TII->ExpandMOVI(MIB, MVT::i32); in INITIALIZE_PASS()
91 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in INITIALIZE_PASS()
93 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8); in INITIALIZE_PASS()
95 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in INITIALIZE_PASS()
98 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in INITIALIZE_PASS()
100 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8); in INITIALIZE_PASS()
102 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in INITIALIZE_PASS()
[all …]
H A DM68kInstrInfo.cpp351 bool M68kInstrInfo::ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const { in ExpandMOVI() argument
352 Register Reg = MIB->getOperand(0).getReg(); in ExpandMOVI()
353 int64_t Imm = MIB->getOperand(1).getImm(); in ExpandMOVI()
363 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to "); in ExpandMOVI()
373 MIB->setDesc(get(M68k::MOVQ)); in ExpandMOVI()
374 MIB->getOperand(0).setReg(SReg); in ExpandMOVI()
377 MIB->setDesc(get(MVTSize == MVT::i16 ? M68k::MOV16ri : M68k::MOV32ri)); in ExpandMOVI()
383 bool M68kInstrInfo::ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst, in ExpandMOVX_RR() argument
386 Register Dst = MIB->getOperand(0).getReg(); in ExpandMOVX_RR()
387 Register Src = MIB->getOperand(1).getReg(); in ExpandMOVX_RR()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h108 MachineInstrBuilder MIB = variable
110 MIB.add(MI->getOperand(1));
111 MIB.addImm(0);
112 MIB.addImm(ARMCC::AL);
113 MIB.addReg(ARM::NoRegister);
115 MachineInstrBuilder MIB = variable
117 MIB.add(MI->getOperand(0));
118 MIB.add(MI->getOperand(1));
119 MIB.addImm(0);
120 MIB.addImm(ARMCC::AL);
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H A DARMInstructionSelector.cpp47 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
145 void renderInvertedImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
233 static bool selectMergeValues(MachineInstrBuilder &MIB, in selectMergeValues() argument
242 Register VReg0 = MIB.getReg(0); in selectMergeValues()
247 Register VReg1 = MIB.getReg(1); in selectMergeValues()
252 Register VReg2 = MIB.getReg(2); in selectMergeValues()
258 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
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/freebsd/tests/sys/kern/
H A Dsysctl_kern_proc.c33 int mib[4], pid_max; in sysctl_kern_proc_all() local
40 mib[0] = CTL_KERN; in sysctl_kern_proc_all()
41 mib[1] = KERN_PROC; in sysctl_kern_proc_all()
42 mib[2] = cmd; in sysctl_kern_proc_all()
44 mib[3] = i; in sysctl_kern_proc_all()
46 if (sysctl(mib, 4, NULL, &sz, NULL, 0) == 0) { in sysctl_kern_proc_all()
49 (void)sysctl(mib, 4, buf, &sz, NULL, 0); in sysctl_kern_proc_all()
54 mib[3] = -1; in sysctl_kern_proc_all()
55 ATF_REQUIRE_ERRNO(ESRCH, sysctl(mib, 4, NULL, &sz, NULL, 0) != 0); in sysctl_kern_proc_all()
66 int cmd, mib[4]; in ATF_TC_BODY() local
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/freebsd/lib/libc/gen/
H A Dsysconf.c75 int mib[2], sverrno, value; in sysconf() local
83 mib[0] = CTL_KERN; in sysconf()
84 mib[1] = KERN_ARGMAX; in sysconf()
99 mib[0] = CTL_KERN; in sysconf()
100 mib[1] = KERN_NGROUPS; in sysconf()
135 mib[0] = CTL_KERN; in sysconf()
136 mib[1] = KERN_SAVED_IDS; in sysconf()
139 mib[0] = CTL_KERN; in sysconf()
140 mib[1] = KERN_POSIX1; in sysconf()
194 mib[0] = CTL_P1003_1B; in sysconf()
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H A D__xuname.c42 int mib[2], rval; in __xuname() local
50 mib[0] = CTL_KERN; in __xuname()
55 mib[1] = KERN_OSTYPE; in __xuname()
58 if (sysctl(mib, 2, q, &len, NULL, 0) == -1) { in __xuname()
68 mib[1] = KERN_HOSTNAME; in __xuname()
71 if (sysctl(mib, 2, q, &len, NULL, 0) == -1) { in __xuname()
83 mib[1] = KERN_OSRELEASE; in __xuname()
86 if (sysctl(mib, 2, q, &len, NULL, 0) == -1) { in __xuname()
104 mib[1] = KERN_VERSION; in __xuname()
107 if (sysctl(mib, 2, q, &len, NULL, 0) == -1) { in __xuname()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp61 void preISelLower(MachineInstr &MI, MachineIRBuilder &MIB,
64 bool replacePtrWithInt(MachineOperand &Op, MachineIRBuilder &MIB,
69 bool selectImplicitDef(MachineInstr &MI, MachineIRBuilder &MIB,
71 bool materializeImm(Register Reg, int64_t Imm, MachineIRBuilder &MIB) const;
72 bool selectAddr(MachineInstr &MI, MachineIRBuilder &MIB,
75 bool selectSExtInreg(MachineInstr &MI, MachineIRBuilder &MIB) const;
76 bool selectSelect(MachineInstr &MI, MachineIRBuilder &MIB,
78 bool selectFPCompare(MachineInstr &MI, MachineIRBuilder &MIB,
81 MachineIRBuilder &MIB) const;
82 bool selectMergeValues(MachineInstr &MI, MachineIRBuilder &MIB,
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H A DRISCVLegalizerInfo.cpp587 MachineIRBuilder &MIB) const { in legalizeVScale()
605 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
606 MIB.buildLShr(Dst, VLENB, MIB.buildConstant(XLenTy, 3 - Log2)); in legalizeVScale()
608 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
609 MIB.buildShl(Dst, VLENB, MIB.buildConstant(XLenTy, Log2 - 3)); in legalizeVScale()
611 MIB.buildInstr(RISCV::G_READ_VLENB, {Dst}, {}); in legalizeVScale()
616 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
617 MIB.buildMul(Dst, VLENB, MIB.buildConstant(XLenTy, Val / 8)); in legalizeVScale()
619 auto VLENB = MIB.buildInstr(RISCV::G_READ_VLENB, {XLenTy}, {}); in legalizeVScale()
620 auto VScale = MIB.buildLShr(XLenTy, VLENB, MIB.buildConstant(XLenTy, 3)); in legalizeVScale()
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/freebsd/sys/dev/bfe/
H A Dif_bfereg.h158 #define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */
188 #define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */
192 #define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */
193 #define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */
194 #define BFE_TX_O 0x00000508 /* MIB TX Octets */
195 #define BFE_TX_P 0x0000050C /* MIB TX Packets */
196 #define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */
197 #define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */
198 #define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */
199 #define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Ddebugfs.c289 phy->mib.dl_cck_cnt, in mt7915_muru_stats_show()
290 phy->mib.dl_ofdm_cnt, in mt7915_muru_stats_show()
291 phy->mib.dl_htmix_cnt, in mt7915_muru_stats_show()
292 phy->mib.dl_htgf_cnt, in mt7915_muru_stats_show()
293 phy->mib.dl_vht_su_cnt); in mt7915_muru_stats_show()
302 phy->mib.dl_vht_2mu_cnt, in mt7915_muru_stats_show()
303 phy->mib.dl_vht_3mu_cnt, in mt7915_muru_stats_show()
304 phy->mib.dl_vht_4mu_cnt); in mt7915_muru_stats_show()
306 sub_total_cnt = phy->mib.dl_vht_2mu_cnt + in mt7915_muru_stats_show()
307 phy->mib.dl_vht_3mu_cnt + in mt7915_muru_stats_show()
[all …]
H A Dmain.c902 struct mt76_mib_stats *mib = &phy->mib; in mt7915_get_stats() local
906 stats->dot11RTSSuccessCount = mib->rts_cnt; in mt7915_get_stats()
907 stats->dot11RTSFailureCount = mib->rts_retries_cnt; in mt7915_get_stats()
908 stats->dot11FCSErrorCount = mib->fcs_err_cnt; in mt7915_get_stats()
909 stats->dot11ACKFailureCount = mib->ack_fail_cnt; in mt7915_get_stats()
1423 struct mt76_mib_stats *mib = &phy->mib; in mt7915_get_et_stats() local
1435 data[ei++] = mib->tx_ampdu_cnt; in mt7915_get_et_stats()
1436 data[ei++] = mib->tx_stop_q_empty_cnt; in mt7915_get_et_stats()
1437 data[ei++] = mib->tx_mpdu_attempts_cnt; in mt7915_get_et_stats()
1438 data[ei++] = mib->tx_mpdu_success_cnt; in mt7915_get_et_stats()
[all …]
/freebsd/sys/x86/pci/
H A Dpci_early_quirks.c45 #define MiB(v) ((unsigned long)(v) << 20) macro
104 return (MiB(1)); in intel_stolen_size_gen3()
106 return (MiB(4)); in intel_stolen_size_gen3()
108 return (MiB(8)); in intel_stolen_size_gen3()
110 return (MiB(16)); in intel_stolen_size_gen3()
112 return (MiB(32)); in intel_stolen_size_gen3()
114 return (MiB(48)); in intel_stolen_size_gen3()
116 return (MiB(64)); in intel_stolen_size_gen3()
118 return (MiB(128)); in intel_stolen_size_gen3()
120 return (MiB(25 in intel_stolen_size_gen3()
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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt792x_mac.c82 struct mt76_mib_stats *mib = &phy->mib; in mt792x_mac_update_mib_stats() local
87 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(0), in mt792x_mac_update_mib_stats()
89 mib->ack_fail_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR3(0), in mt792x_mac_update_mib_stats()
91 mib->ba_miss_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR2(0), in mt792x_mac_update_mib_stats()
93 mib->rts_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR0(0), in mt792x_mac_update_mib_stats()
95 mib->rts_retries_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR1(0), in mt792x_mac_update_mib_stats()
98 mib->tx_ampdu_cnt += mt76_rr(dev, MT_MIB_SDR12(0)); in mt792x_mac_update_mib_stats()
99 mib->tx_mpdu_attempts_cnt += mt76_rr(dev, MT_MIB_SDR14(0)); in mt792x_mac_update_mib_stats()
100 mib->tx_mpdu_success_cnt += mt76_rr(dev, MT_MIB_SDR15(0)); in mt792x_mac_update_mib_stats()
103 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR9_EBF_CNT_MASK, val); in mt792x_mac_update_mib_stats()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp557 MachineInstrBuilder MIB = in selectG_MERGE_VALUES() local
561 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
562 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
702 auto MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg) in selectG_BUILD_VECTOR() local
705 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) in selectG_BUILD_VECTOR()
708 MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst) in selectG_BUILD_VECTOR()
712 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) in selectG_BUILD_VECTOR()
753 auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst) in selectG_BUILD_VECTOR() local
759 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_BUILD_VECTOR()
861 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), DstReg) in selectG_SBFX_UBFX() local
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/freebsd/crypto/openssl/crypto/
H A Dia64cpuid.S20 { .mib; br.ret.sptk.many b0 };;
26 { .mib; mov r8=ar.itc
44 { .mib; cmp.ne p6,p0=r2,r3
47 { .mib; nop.m 0
67 { .mib; alloc r2=ar.pfs,0,96,0,96
137 { .mib; mov r8=sp
145 { .mib; cmp.eq p6,p0=0,r33 // len==0
148 { .mib; and r2=7,r32
153 { .mib; st1 [r32]=r0,1
160 { .mib; cmp.eq p6,p0=0,r2
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h124 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument
127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
143 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
148 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) { in addOffset() argument
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
157 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
164 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp45 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) { in insertInstr() argument
46 getMBB().insert(getInsertPt(), MIB); in insertInstr()
47 recordInsertion(MIB); in insertInstr()
48 return MIB; in insertInstr()
100 auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE); in buildConstDbgValue() local
111 MIB.addCImm(CI); in buildConstDbgValue()
113 MIB.addImm(CI->getZExtValue()); in buildConstDbgValue()
115 MIB.addFPImm(CFP); in buildConstDbgValue()
117 MIB.addImm(0); in buildConstDbgValue()
120 MIB.addReg(Register()); in buildConstDbgValue()
[all …]
/freebsd/contrib/jemalloc/src/
H A Dctl.c50 static int n##_ctl(tsd_t *tsd, const size_t *mib, size_t miblen, \
55 const size_t *mib, size_t miblen, size_t i);
1297 size_t mib[CTL_MAX_DEPTH]; in ctl_byname() local
1306 ret = ctl_lookup(tsd_tsdn(tsd), name, nodes, mib, &depth); in ctl_byname()
1313 ret = node->ctl(tsd, mib, depth, oldp, oldlenp, newp, newlen); in ctl_byname()
1338 ctl_bymib(tsd_t *tsd, const size_t *mib, size_t miblen, void *oldp, in ctl_bymib() argument
1356 if (node->nchildren <= mib[i]) { in ctl_bymib()
1360 node = ctl_named_children(node, mib[i]); in ctl_bymib()
1366 node = inode->index(tsd_tsdn(tsd), mib, miblen, mib[i]); in ctl_bymib()
1376 ret = node->ctl(tsd, mib, miblen, oldp, oldlenp, newp, newlen); in ctl_bymib()
[all …]
/freebsd/usr.sbin/bsnmpd/modules/snmp_lm75/
H A Dsnmp_lm75.c85 "This module implements the BEGEMOT MIB for reading LM75 sensors data.",
109 "The MIB module for reading lm75 sensors data.", module); in lm75_start()
137 int mib[12]; in sysctlname() local
139 if (nlen > (int)(sizeof(mib) / sizeof(int) - 2)) in sysctlname()
142 mib[0] = 0; in sysctlname()
143 mib[1] = 1; in sysctlname()
144 memcpy(mib + 2, oid, nlen * sizeof(int)); in sysctlname()
146 if (sysctl(mib, nlen + 2, name, &len, 0, 0) == -1) in sysctlname()
155 int mib[12]; in sysctlgetnext() local
157 if (nlen > (int)(sizeof(mib) / sizeof(int) - 2)) in sysctlgetnext()
[all …]
/freebsd/usr.sbin/bsnmpd/modules/snmp_bridge/
H A Dsnmp_bridge.337 module implements the BRIDGE-MIB as standardized in RFC 4188, the RSTP-MIB
38 standardized in RFC4318 and a private BEGEMOT-BRIDGE-MIB, which allows
40 Most of the objects defined in the private BEGEMOT-BRIDGE-MIB are duplicates
41 of the original objects defined by the standard BRIDGE-MIB, but the private
101 The description of the MIB tree implemented by
103 .It Pa /usr/share/snmp/mibs/BRIDGE-MIB.txt
104 This is the BRIDGE-MIB that is implemented by this module.
105 .It Pa /usr/share/snmp/mibs/RSTP-MIB.txt
106 This is the RSTP-MIB implemented by this module.
107 .It Pa /usr/share/snmp/mibs/BEGEMOT-BRIDGE-MIB.txt
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/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp92 MachineIRBuilder MIB(MF); in addConstantsToTrack() local
94 GR->getOrCreateSPIRVType(Const->getType(), MIB); in addConstantsToTrack()
169 MachineIRBuilder MIB) { in insertBitcasts() argument
172 static_cast<const SPIRVSubtarget *>(&MIB.getMF().getSubtarget()); in insertBitcasts()
180 MIB.setInsertPt(*MI.getParent(), MI); in insertBitcasts()
183 MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg()); in insertBitcasts()
189 SPIRVType *BaseTy = GR->getOrCreateSPIRVType(ElemTy, MIB); in insertBitcasts()
198 if (MachineInstr *AssignMI = findAssignTypeInstr(Def, MIB.getMRI())) in insertBitcasts()
200 MIB.getMRI()->replaceRegWith(Def, Source); in insertBitcasts()
203 MIB.buildBitcast(Def, Source); in insertBitcasts()
[all …]
/freebsd/contrib/llvm-project/compiler-rt/lib/memprof/
H A Dmemprof_rawprofile.cpp29 void RecordStackId(const uptr Key, UNUSED LockedMemInfoBlock *const &MIB, in RecordStackId() argument
31 // No need to touch the MIB value here since we are only recording the key. in RecordStackId()
143 // The MIB section has the following format:
144 // ---------- MIB Info
146 // ---------- MIB Entry 0
152 // ---------- MIB Entry 1
172 Ptr = WriteBytes((*h)->mib, Ptr); in SerializeMIBInfoToBuffer()
173 for (u64 j = 0; j < (*h)->mib.AccessHistogramSize; ++j) { in SerializeMIBInfoToBuffer()
174 u64 HistogramEntry = ((u64 *)((*h)->mib.AccessHistogram))[j]; in SerializeMIBInfoToBuffer()
177 if ((*h)->mib.AccessHistogramSize > 0) { in SerializeMIBInfoToBuffer()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp187 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument
225 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
238 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
250 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
317 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument
329 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
381 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand()
383 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand()
384 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand()
391 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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