108     MachineInstrBuilder MIB =  variable
110     MIB.add(MI->getOperand(1));
111     MIB.addImm(0);
112     MIB.addImm(ARMCC::AL);
113     MIB.addReg(ARM::NoRegister);
115     MachineInstrBuilder MIB =  variable
117     MIB.add(MI->getOperand(0));
118     MIB.add(MI->getOperand(1));
119     MIB.addImm(0);
120     MIB.addImm(ARMCC::AL);
121     MIB.addReg(ARM::NoRegister);
122     MIB.addReg(ARM::CPSR, RegState::Define);
126   MachineInstrBuilder MIB =  variable
128   MIB.addMBB(getWhileLoopStartTargetBB(*MI)); // branch target
129   MIB.addImm(ARMCC::EQ);                      // condition code
130   MIB.addReg(ARM::CPSR);
149   MachineInstrBuilder MIB =  variable
151   MIB.add(MI->getOperand(0));
152   MIB.add(MI->getOperand(1));
153   MIB.add(MI->getOperand(2));
154   MIB.addImm(ARMCC::AL);
155   MIB.addReg(0);
158     MIB.addReg(ARM::CPSR);
159     MIB->getOperand(5).setIsDef(true);
161     MIB.addReg(0);
173     MachineInstrBuilder MIB =  variable
175     MIB.add(MI->getOperand(0));
176     MIB.addImm(0);
177     MIB.addImm(ARMCC::AL);
178     MIB.addReg(ARM::NoRegister);
182   MachineInstrBuilder MIB =  variable
184   MIB.add(MI->getOperand(1)); // branch target
185   MIB.addImm(ARMCC::NE);      // condition code
186   MIB.addReg(ARM::CPSR);