| /linux/drivers/mailbox/ |
| H A D | Kconfig | 2 menuconfig MAILBOX config
3 bool "Mailbox Hardware Support"
5 Mailbox is a framework to control hardware communication between
9 if MAILBOX
12 tristate "ARM MHU Mailbox"
16 The controller has 3 mailbox channels, the last of which can be
20 tristate "ARM MHUv2 Mailbox"
27 tristate "ARM MHUv3 Mailbox"
40 tristate "i.MX Mailbox"
43 Mailbox implementation for i.MX Messaging Unit (MU).
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| H A D | Makefile | 2 # Generic MAILBOX API
4 obj-$(CONFIG_MAILBOX) += mailbox.o
6 obj-$(CONFIG_MAILBOX_TEST) += mailbox-test.o
14 obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o
16 obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) += armada-37xx-rwtm-mailbox.o
22 obj-$(CONFIG_OMAP2PLUS_MBOX) += omap-mailbox.o
24 obj-$(CONFIG_ROCKCHIP_MBOX) += rockchip-mailbox.o
28 obj-$(CONFIG_ALTERA_MBOX) += mailbox-altera.o
30 obj-$(CONFIG_BCM2835_MBOX) += bcm2835-mailbox.o
32 obj-$(CONFIG_STI_MBOX) += mailbox-sti.o
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| /linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | ti,omap-mailbox.yaml | 4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
7 title: TI OMAP2+ and K3 Mailbox devices
13 The OMAP Mailbox hardware facilitates communication between different
14 processors using a queued mailbox interrupt mechanism. The IP block is
19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and
46 Mailbox Controller Nodes
48 A Mailbox device node is used to represent a Mailbox IP instance/cluster
52 Mailbox Users
55 them using the common mailbox binding properties, "mboxes" and the optional
56 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
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| H A D | hisilicon,hi6220-mailbox.txt | 1 Hisilicon Hi6220 Mailbox Driver
4 Hisilicon Hi6220 mailbox supports up to 32 channels. Each channel
9 Mailbox Device Node:
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
20 of cells required for the mailbox specifier. Must be 3.
22 phandle: Label name of mailbox controller
27 mailbox driver uses it to acknowledge interrupt
28 - interrupts: Contains the interrupt information for the mailbox
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
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| H A D | mailbox.txt | 1 * Generic Mailbox Controller and client driver bindings
3 Generic binding to provide a way for Mailbox controller drivers to
4 assign appropriate mailbox channel to client drivers.
6 * Mailbox Controller
9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
13 mailbox: mailbox {
19 * Mailbox Client
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
27 users of these mailboxes for IPC, one for each mailbox. This shared
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| H A D | apple,mailbox.yaml | 4 $id: http://devicetree.org/schemas/mailbox/apple,mailbox.yaml#
7 title: Apple Mailbox Controller
14 The Apple mailbox consists of two FIFOs used to exchange 64+32 bit
16 of this mailbox can be found on Apple SoCs.
31 - apple,t8103-asc-mailbox
32 - apple,t8112-asc-mailbox
33 - apple,t6000-asc-mailbox
34 - const: apple,asc-mailbox-v4
42 - apple,t8103-m3-mailbox
43 - apple,t8112-m3-mailbox
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| H A D | xlnx,zynqmp-ipi-mailbox.yaml | 4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
7 title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
10 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
41 - xlnx,zynqmp-ipi-mailbox
42 - xlnx,versal-ipi-mailbox
71 Remote Xilinx IPI agent ID of which the mailbox is connected to.
80 '^mailbox@[0-9a-f]+$':
81 description: Internal ipi mailbox node
88 - xlnx,zynqmp-ipi-dest-mailbox
89 - xlnx,versal-ipi-dest-mailbox
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| H A D | altera-mailbox.txt | 1 Altera Mailbox Driver
5 - compatible : "altr,mailbox-1.0".
6 - reg : physical base address of the mailbox and length of
8 - #mbox-cells: Common mailbox binding property to identify the number
9 of cells required for the mailbox specifier. Should be 1.
16 mbox_tx: mailbox@100 {
17 compatible = "altr,mailbox-1.0";
24 mbox_rx: mailbox@200 {
25 compatible = "altr,mailbox-1.0";
32 Mailbox client
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| H A D | microchip,mpfs-mailbox.yaml | 4 $id: http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
14 const: microchip,mpfs-mailbox
19 - description: mailbox control & data registers
20 - description: mailbox interrupt registers
23 - description: mailbox control registers
24 - description: mailbox interrupt registers
25 - description: mailbox data registers
46 mbox: mailbox@37020000 {
47 compatible = "microchip,mpfs-mailbox";
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| H A D | xgene-slimpro-mailbox.txt | 1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
6 There are total of 8 interrupts in this mailbox. Each used for an individual
7 door bell (or mailbox channel).
12 - reg: Contains the mailbox register address range.
15 the interrupt for mailbox channel 0 and interrupt 1 for
16 mailbox channel 1 and so likewise for the reminder.
18 - #mbox-cells: only one to specify the mailbox channel number.
22 Mailbox Node:
23 mailbox: mailbox@10540000 {
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| H A D | mediatek,gce-props.yaml | 4 $id: http://devicetree.org/schemas/mailbox/mediatek,gce-props.yaml#
15 (CMDQ) mailbox driver is a driver for GCE, implemented using the Linux
16 mailbox framework. It is used to receive messages from mailbox consumers
18 We use mediatek,gce-mailbox.yaml to define the properties for CMDQ mailbox
20 registers is a mailbox consumer. The mailbox consumer can request a mailbox
22 that the GCE thread to configure its hardware. The mailbox provider can also
23 reserve a mailbox channel to configure GCE hardware register by the specific
24 GCE thread. This binding defines the common GCE properties for both mailbox
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| /linux/drivers/net/ethernet/mellanox/mlx4/ |
| H A D | fw_qos.c | 87 struct mlx4_cmd_mailbox *mailbox; in mlx4_SET_PORT_PRIO2TC() local
93 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_SET_PORT_PRIO2TC()
94 if (IS_ERR(mailbox)) in mlx4_SET_PORT_PRIO2TC()
95 return PTR_ERR(mailbox); in mlx4_SET_PORT_PRIO2TC()
97 context = mailbox->buf; in mlx4_SET_PORT_PRIO2TC()
103 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, in mlx4_SET_PORT_PRIO2TC()
106 mlx4_free_cmd_mailbox(dev, mailbox); in mlx4_SET_PORT_PRIO2TC()
114 struct mlx4_cmd_mailbox *mailbox; in mlx4_SET_PORT_SCHEDULER() local
120 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_SET_PORT_SCHEDULER()
121 if (IS_ERR(mailbox)) in mlx4_SET_PORT_SCHEDULER()
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| H A D | mcg.c | 54 struct mlx4_cmd_mailbox *mailbox, in mlx4_QP_FLOW_STEERING_ATTACH() argument
61 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0, in mlx4_QP_FLOW_STEERING_ATTACH()
83 struct mlx4_cmd_mailbox *mailbox) in mlx4_READ_ENTRY() argument
85 return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG, in mlx4_READ_ENTRY()
90 struct mlx4_cmd_mailbox *mailbox) in mlx4_WRITE_ENTRY() argument
92 return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG, in mlx4_WRITE_ENTRY()
97 struct mlx4_cmd_mailbox *mailbox) in mlx4_WRITE_PROMISC() argument
102 return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1, in mlx4_WRITE_PROMISC()
107 static int mlx4_GID_HASH(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_GID_HASH() argument
113 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, 0, op_mod, in mlx4_GID_HASH()
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| H A D | srq.c | 64 static int mlx4_SW2HW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_SW2HW_SRQ() argument
67 return mlx4_cmd(dev, mailbox->dma, srq_num, 0, in mlx4_SW2HW_SRQ()
72 static int mlx4_HW2SW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_HW2SW_SRQ() argument
75 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, srq_num, in mlx4_HW2SW_SRQ()
76 mailbox ? 0 : 1, MLX4_CMD_HW2SW_SRQ, in mlx4_HW2SW_SRQ()
86 static int mlx4_QUERY_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_QUERY_SRQ() argument
89 return mlx4_cmd_box(dev, 0, mailbox->dma, srq_num, 0, MLX4_CMD_QUERY_SRQ, in mlx4_QUERY_SRQ()
166 struct mlx4_cmd_mailbox *mailbox; in mlx4_srq_alloc() local
181 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_srq_alloc()
182 if (IS_ERR(mailbox)) { in mlx4_srq_alloc()
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| /linux/drivers/net/ethernet/intel/ice/ |
| H A D | ice_vf_mbx.c | 17 * Send message to VF driver (0x0802) using mailbox
86 /* The mailbox overflow detection algorithm helps to check if there
89 * 1. The mailbox snapshot structure, ice_mbx_snapshot, is initialized during
92 * messages within the mailbox queue while looking for a malicious VF.
94 * 2. When the caller starts processing its mailbox queue in response to an
120 * in ice_mbx_snapshot for every new mailbox interrupt handled.
129 * ice_mbx_reset_snapshot - Reset mailbox snapshot structure
130 * @snap: pointer to the mailbox snapshot
136 /* Clear mbx_buf in the mailbox snaphot structure and setting the in ice_mbx_reset_snapshot()
137 * mailbox snapshot state to a new capture. in ice_mbx_reset_snapshot()
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| /linux/drivers/scsi/lpfc/ |
| H A D | lpfc_mbox.c | 47 * lpfc_mbox_rsrc_prep - Prepare a mailbox with DMA buffer memory.
49 * @mbox: pointer to the driver internal queue element for mailbox command.
51 * A mailbox command consists of the pool memory for the command, @mbox, and
86 * lpfc_mbox_rsrc_cleanup - Free the mailbox DMA buffer and virtual memory.
88 * @mbox: pointer to the driver internal queue element for mailbox command.
91 * A mailbox command consists of the pool memory for the command, @mbox, and
123 * @pmb: pointer to the driver internal queue element for mailbox command.
126 * The dump mailbox command provides a method for the device driver to obtain
129 * This routine prepares the mailbox command for dumping list of static
150 /* For SLI3 HBAs data is embedded in mailbox */ in lpfc_dump_static_vport()
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| /linux/arch/arm64/kernel/ |
| H A D | acpi_parking_protocol.c | 21 struct parking_protocol_mailbox __iomem *mailbox; member
62 struct parking_protocol_mailbox __iomem *mailbox; in acpi_parking_protocol_cpu_boot() local
66 * Map mailbox memory with attribute device nGnRE (ie ioremap - in acpi_parking_protocol_cpu_boot()
71 * If the mailbox is mistakenly allocated in the linear mapping in acpi_parking_protocol_cpu_boot()
76 mailbox = ioremap(cpu_entry->mailbox_addr, sizeof(*mailbox)); in acpi_parking_protocol_cpu_boot()
77 if (!mailbox) in acpi_parking_protocol_cpu_boot()
80 cpu_id = readl_relaxed(&mailbox->cpu_id); in acpi_parking_protocol_cpu_boot()
82 * Check if firmware has set-up the mailbox entry properly in acpi_parking_protocol_cpu_boot()
86 iounmap(mailbox); in acpi_parking_protocol_cpu_boot()
91 * stash the mailbox address mapping to use it for further FW in acpi_parking_protocol_cpu_boot()
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| /linux/drivers/infiniband/hw/mthca/ |
| H A D | mthca_cmd.c | 468 /* Invoke a command with an output mailbox */
612 struct mthca_mailbox *mailbox; in mthca_alloc_mailbox() local
614 mailbox = kmalloc(sizeof *mailbox, gfp_mask); in mthca_alloc_mailbox()
615 if (!mailbox) in mthca_alloc_mailbox()
618 mailbox->buf = dma_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma); in mthca_alloc_mailbox()
619 if (!mailbox->buf) { in mthca_alloc_mailbox()
620 kfree(mailbox); in mthca_alloc_mailbox()
624 return mailbox; in mthca_alloc_mailbox()
627 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox) in mthca_free_mailbox() argument
629 if (!mailbox) in mthca_free_mailbox()
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| H A D | mthca_mcg.c | 67 struct mthca_mailbox *mailbox; in find_mgm() local
72 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); in find_mgm()
73 if (IS_ERR(mailbox)) in find_mgm()
75 mgid = mailbox->buf; in find_mgm()
79 err = mthca_MGID_HASH(dev, mailbox, hash); in find_mgm()
116 mthca_free_mailbox(dev, mailbox); in find_mgm()
123 struct mthca_mailbox *mailbox; in mthca_multicast_attach() local
131 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); in mthca_multicast_attach()
132 if (IS_ERR(mailbox)) in mthca_multicast_attach()
133 return PTR_ERR(mailbox); in mthca_multicast_attach()
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| /linux/drivers/net/ethernet/intel/fm10k/ |
| H A D | fm10k_mbx.c | 125 * @mbx: pointer to mailbox
145 * @mbx: pointer to mailbox
161 * @mbx: pointer to mailbox
177 * @mbx: pointer to mailbox
193 * @mbx: pointer to mailbox
209 * @mbx: pointer to mailbox
290 * @mbx: pointer to mailbox
294 * the start of a message larger than the mailbox is detected.
324 * @mbx: pointer to mailbox
327 * mailbox memory. The offset in mbmem is based on the lower bits of the
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| H A D | fm10k_mbx.h | 13 /* PF Mailbox Registers */
32 /* VF Mailbox Registers */
43 /* PF/VF Mailbox state machine
58 * The diagram above describes the PF/VF mailbox state machine. There
60 * Closed: This state represents a mailbox that is in a standby state
61 * with interrupts disabled. In this state the mailbox should not
62 * read the mailbox or write any data. The only means of exiting
64 * mailbox, it will then transition to the connect state.
65 * Connect: In this state the mailbox is seeking a connection. It will
67 * wait for a reply from the other side of the mailbox. This state
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| /linux/drivers/net/ethernet/intel/igb/ |
| H A D | e1000_mbx.c | 7 * igb_read_mbx - Reads a message from the mailbox
11 * @mbx_id: id of mailbox to read
22 /* limit read to size of mailbox */ in igb_read_mbx()
33 * igb_write_mbx - Write a message to the mailbox
37 * @mbx_id: id of mailbox to write
58 * @mbx_id: id of mailbox to check
76 * @mbx_id: id of mailbox to check
94 * @mbx_id: id of mailbox to check
110 * igb_unlock_mbx - unlock the mailbox
112 * @mbx_id: id of mailbox to check
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| /linux/drivers/scsi/csiostor/ |
| H A D | csio_mb.c | 51 * csio_mb_fw_retval - FW return value from a mailbox response.
52 * @mbp: Mailbox structure
68 * @mbp: Mailbox structure
69 * @m_mbox: Master mailbox number, if any.
70 * @a_mbox: Mailbox number for asycn notifications.
101 * @mbp: Mailbox structure
102 * @retval: Mailbox return value from Firmware
135 * @mbp: Mailbox structure
156 * @mbp: Mailbox structure
181 * @mbp: Mailbox structure
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| /linux/drivers/net/ethernet/intel/ixgbe/ |
| H A D | ixgbe_mbx.c | 10 * ixgbe_read_mbx - Reads a message from the mailbox
14 * @mbx_id: id of mailbox to read
22 /* limit read to size of mailbox */ in ixgbe_read_mbx()
33 * ixgbe_write_mbx - Write a message to the mailbox
37 * @mbx_id: id of mailbox to write
57 * @mbx_id: id of mailbox to check
74 * @mbx_id: id of mailbox to check
91 * @mbx_id: id of mailbox to check
108 * @mbx_id: id of mailbox to write
133 * @mbx_id: id of mailbox to write
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| /linux/drivers/infiniband/hw/hns/ |
| H A D | hns_roce_cmd.c | 64 "failed to post mailbox 0x%x in poll mode, ret = %d.\n", in __hns_roce_cmd_mbox_poll()
135 "failed to post mailbox 0x%x in event mode, ret = %d.\n", in __hns_roce_cmd_mbox_wait()
142 dev_err_ratelimited(dev, "[cmd] token 0x%x mailbox 0x%x timeout.\n", in __hns_roce_cmd_mbox_wait()
150 dev_err_ratelimited(dev, "[cmd] token 0x%x mailbox 0x%x error %d.\n", in __hns_roce_cmd_mbox_wait()
255 struct hns_roce_cmd_mailbox *mailbox; in hns_roce_alloc_cmd_mailbox() local
257 mailbox = kmalloc(sizeof(*mailbox), GFP_KERNEL); in hns_roce_alloc_cmd_mailbox()
258 if (!mailbox) in hns_roce_alloc_cmd_mailbox()
261 mailbox->buf = in hns_roce_alloc_cmd_mailbox()
262 dma_pool_alloc(hr_dev->cmd.pool, GFP_KERNEL, &mailbox->dma); in hns_roce_alloc_cmd_mailbox()
263 if (!mailbox->buf) { in hns_roce_alloc_cmd_mailbox()
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