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/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
[all …]
/linux/drivers/iommu/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 tristate "ARM Ltd. System MMU (SMMU) Support"
11 Support for implementations of the ARM System MMU architecture
19 bool "Support the legacy \"mmu-masters\" devicetree bindings"
22 Support for the badly designed and deprecated "mmu-masters"
36 securely, and you don't want to boot with the 'arm-smmu.disable_bypass=0'
40 Note that 'arm-smmu.disable_bypass=1' will still take precedence.
47 MMU-500's next-page prefetcher for sake of 4 known errata.
51 Refer silicon-errata.rst for info on errata IDs.
77 tristate "ARM Ltd. System MMU Version 3 (SMMUv3) Support"
[all …]
/linux/arch/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
10 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
12 select ARCH_HAS_DEBUG_VIRTUAL if MMU
13 select ARCH_HAS_DMA_ALLOC if MMU
26 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
27 select ARCH_HAS_STRICT_MODULE_RWX if MMU
30 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
47 # https://github.com/llvm/llvm-project/commit/d130f402642fba3d065aacb506cb061c899558de
49 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
54 select BUILDTIME_TABLE_SORT if MMU
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/linux/drivers/gpu/drm/gma500/
H A Dpsb_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2007-2011, Intel Corporation.
45 * to the different groups of PowerVR 5-series chip designs
49 * PowerVR SGX535 - Poulsbo - Intel GMA 500, Intel Atom Z5xx
50 * PowerVR SGX535 - Moorestown - Intel GMA 600
51 * PowerVR SGX535 - Oaktrail - Intel GMA 600, Intel Atom Z6xx, E6xx
52 * PowerVR SGX545 - Cedartrail - Intel GMA 3600, Intel Atom D2500, N2600
53 * PowerVR SGX545 - Cedartrail - Intel GMA 3650, Intel Atom D2550, D2700,
98 * psb_spank - reset the 2D engine
124 PSB_WSGX32(dev_priv->gtt.gatt_start, PSB_CR_BIF_TWOD_REQ_BASE); in psb_spank()
[all …]
/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Dadreno_gpu.c1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/nvmem-consumer.h>
33 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt()
45 return -EINVAL; in zap_shader_load_mdt()
48 np = of_get_child_by_name(dev->of_node, "zap-shader"); in zap_shader_load_mdt()
51 return -ENODEV; in zap_shader_load_mdt()
62 * Check for a firmware-name property. This is the new scheme in zap_shader_load_mdt()
67 * If the firmware-name property is found, we bypass the in zap_shader_load_mdt()
71 * If the firmware-name property is not found, for backwards in zap_shader_load_mdt()
75 of_property_read_string_index(np, "firmware-name", 0, &signed_fwname); in zap_shader_load_mdt()
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/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-nvidia.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 NVIDIA CORPORATION. All rights reserved.
12 #include "arm-smmu.h"
15 * Tegra194 has three ARM MMU-500 Instances.
18 * non-isochronous HW devices.
23 * memory client. This is necessary to allow for use-case such as seamlessly
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
69 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg()
90 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg64()
108 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { in nvidia_smmu_tlb_sync()
[all …]
H A Darm-smmu.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * - SMMUv1 and v2 implementations
11 * - Stream-matching and stream-indexing
12 * - v7/v8 long-descriptor format
13 * - Non-secure access to the SMMU
14 * - Context fault reporting
15 * - Extended Stream ID (16 bit)
18 #define pr_fmt(fmt) "arm-smmu: " fmt
24 #include <linux/dma-mapping.h>
41 #include "arm-smmu.h"
[all …]
/linux/drivers/gpu/drm/panfrost/
H A Dpanfrost_job.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-resv.h>
25 #define JOB_TIMEOUT_MS 500
27 #define job_write(dev, reg, data) writel(data, dev->iomem + (reg))
28 #define job_read(dev, reg) readl(dev->iomem + (reg))
71 switch (f->queue) { in panfrost_fence_get_timeline_name()
73 return "panfrost-js-0"; in panfrost_fence_get_timeline_name()
75 return "panfrost-js-1"; in panfrost_fence_get_timeline_name()
77 return "panfrost-js-2"; in panfrost_fence_get_timeline_name()
91 struct panfrost_job_slot *js = pfdev->js; in panfrost_fence_create()
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/linux/drivers/bus/
H A Darm-cci.c17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
67 #define DRIVER_NAME "ARM-CCI"
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/linux/drivers/accel/habanalabs/goya/
H A Dgoya.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
9 #include "../include/hw_ip/mmu/mmu_general.h"
10 #include "../include/hw_ip/mmu/mmu_v1_0.h"
23 * - Range registers (When MMU is enabled, DMA RR does NOT protect host)
24 * - MMU
27 * - Range registers (protect the first 512MB)
28 * - MMU (isolation between users)
31 * - Range registers
32 * - Protection bits
[all …]
/linux/drivers/clocksource/
H A Dhyperv_timer.c1 // SPDX-License-Identifier: GPL-2.0
5 * provided by the Hyper-V hypervisor to guest VMs, as described
6 * in the Hyper-V Top Level Functional Spec (TLFS). This driver
37 * mechanism is used when running on older versions of Hyper-V
38 * that don't support Direct Mode. While Hyper-V provides
39 * four stimer's per CPU, Linux uses only stimer0.
45 * However, for legacy versions of Hyper-V when Direct Mode
52 static int stimer0_irq = -1;
65 ce->event_handler(ce); in hv_stimer0_isr()
71 * per-cpu interrupts, which also implies Direct Mode.
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/device/
H A Dpci.c17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
846 { 0x00fd, "Quadro FX 330/Quadro NVS 280 PCI-E" },
888 { 0x0173, "GeForce4 MX 440-SE" },
896 { 0x017c, "Quadro4 500 GoGL" },
930 { 0x0202, "GeForce3 Ti 500" },
937 { 0x0222, "GeForce 6200 A-LE" },
942 { 0x0245, "Quadro NVS 210S / GeForce 6150LE" },
997 { 0x032b, "Quadro FX 500/FX 600" },
1126 { 0x0630, "GeForce 9700 S" },
1168 { 0x06df, "Tesla M2070-Q" },
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015-2018 Etnaviv Project
9 #include <linux/dma-fence.h>
10 #include <linux/dma-mapping.h>
32 { .name = "etnaviv-gpu,2d" },
42 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
46 *value = gpu->identity.model; in etnaviv_gpu_get_param()
50 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
54 *value = gpu->identity.features; in etnaviv_gpu_get_param()
58 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
[all …]
/linux/kernel/trace/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 API, which will be used by other function-entry hooking
27 See Documentation/trace/ftrace-design.rst
32 See Documentation/trace/ftrace-design.rst
45 See Documentation/trace/ftrace-design.rst
86 See Documentation/trace/ftrace-design.rst
91 Arch supports the gcc options -pg with -mfentry
96 Arch supports the gcc options -pg with -mrecord-mcount and -nop-mcount
101 Arch supports objtool --mcount
106 Arch supports the objtool options --mcount with --mnop.
[all …]
/linux/arch/x86/kvm/vmx/
H A Dvmx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
50 #include <asm/spec-ctrl.h>
63 #include "mmu.h"
77 #include "mmu/spte.h"
80 MODULE_DESCRIPTION("KVM support for VMX (Intel VT-x) extensions");
143 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
170 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
186 /* Default doubles per-vcpu window every exit. */
[all …]
/linux/drivers/usb/gadget/udc/
H A Dat91_udc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * at91_udc -- driver for at91-series USB peripheral controller
33 #include <linux/mfd/syscon/atmel-matrix.h>
39 * This controller is simple and PIO-only. It's used in many AT91-series
40 * full speed USB controllers, including the at91rm9200 (arm920T, with MMU),
41 * at91sam926x (arm926ejs, with MMU), and several no-mmu versions.
47 * The pullup is most important (so it's integrated on sam926x parts). It
76 EP_INFO("ep3-int",
91 __raw_readl((udc)->udp_baseaddr + (reg))
93 __raw_writel((val), (udc)->udp_baseaddr + (reg))
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm6125.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dispcc-sm6125.h>
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-sm6125.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
16 interrupt-parent = <&intc>;
[all …]
H A Dsdx75.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,icc.h>
14 #include <dt-bindings/interconnect/qcom,sdx75.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/mailbox/qcom-ipcc.h>
17 #include <dt-bindings/power/qcom,rpmhpd.h>
[all …]
H A Dqdu1000.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interconnect/qcom,icc.h>
11 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
[all …]
H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
8 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
[all …]
H A Dsdm670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
12 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
13 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
[all …]
/linux/drivers/video/fbdev/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 a well-defined interface, so the software doesn't need to know
15 anything about the low-level (hardware register) stuff.
21 On several non-X86 architectures, the frame buffer device is the
29 and the Framebuffer-HOWTO at
30 <http://www.munted.org.uk/programming/Framebuffer-HOWTO-1.3.html> for more
40 are compiling a kernel for a non-x86 architecture.
46 device-aware may cause unexpected results. If unsure, say N.
57 Common utility functions useful to fbdev drivers of VGA-based
82 If you have a PCI-based system, this enables support for these
[all …]
/linux/drivers/mtd/chips/
H A Dcfi_cmdset_0002.c1 // SPDX-License-Identifier: GPL-2.0
118 * CFI Primary Vendor-Specific Extended Query table 1.5
122 struct cfi_pri_amdstd *extp = cfi->cmdset_priv; in cfi_use_status_reg()
125 return extp && extp->MinorVersion >= '5' && in cfi_use_status_reg()
126 (extp->SoftwareFeatures & poll_mask) == CFI_POLL_STATUS_REG; in cfi_use_status_reg()
132 struct cfi_private *cfi = map->fldrv_priv; in cfi_check_err_status()
138 cfi_send_gen_cmd(0x70, cfi->addr_unlock1, chip->start, map, cfi, in cfi_check_err_status()
139 cfi->device_type, NULL); in cfi_check_err_status()
142 /* The error bits are invalid while the chip's busy */ in cfi_check_err_status()
150 pr_err("%s erase operation failed, status %lx\n", in cfi_check_err_status()
[all …]
/linux/drivers/comedi/drivers/
H A Ds626.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
68 * struct s626_private - Working data for s626 driver.
69 * @ai_cmd_running: non-zero if ai_cmd is running.
98 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
102 * Enable/disable a function or test status bit(s) that are accessed
110 writel(val, dev->mmio + reg); in s626_mc_enable()
116 writel(cmd << 16, dev->mmio + reg); in s626_mc_disable()
124 val = readl(dev->mmio + reg); in s626_mc_test()
[all …]

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