Home
last modified time | relevance | path

Searched +full:mipi +full:- +full:dsi (Results 1 – 25 of 173) sorted by relevance

1234567

/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun6i-a31-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI-DSI Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - enum:
17 - allwinner,sun6i-a31-mipi-dsi
18 - allwinner,sun50i-a64-mipi-dsi
[all …]
H A Damlogic,meson-g12a-dw-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-g12a-dw-mipi-dsi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller
11 - Neil Armstrong <neil.armstrong@linaro.org>
15 - A Synopsys DesignWare MIPI DSI Host Controller IP
16 - A TOP control block controlling the Clocks & Resets of the IP
19 - $ref: dsi-controller.yaml#
24 - amlogic,meson-g12a-dw-mipi-dsi
[all …]
/linux/drivers/gpu/drm/panel/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 Y030XX067A 320x480 3.0" panel as found in the YLM RG-280M, RG-300
18 and RG-99 handheld gaming consoles.
46 as found in the YLM RS-97 handheld gaming console.
49 tristate "Boe BF060Y8M-AJ0 panel"
54 Say Y here if you want to enable support for Boe BF060Y8M-AJ0
56 uses 24 bit RGB per pixel. It provides a MIPI DSI interface to
57 the host and backlight is controlled through DSI commands.
66 TFT-LCD modules. The panel has a 1200x1920 resolution and uses
67 24 bit RGB per pixel. It provides a MIPI DSI interface to
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dintel,keembay-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/intel,keembay-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Keem Bay mipi dsi controller
10 - Anitha Chrisanthus <anitha.chrisanthus@intel.com>
11 - Edmond J Dea <edmund.j.dea@intel.com>
15 const: intel,keembay-dsi
19 - description: MIPI registers range
21 reg-names:
[all …]
H A Drenesas,dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L MIPI DSI Encoder
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This binding describes the MIPI DSI encoder embedded in the Renesas
14 RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
18 - $ref: /schemas/display/dsi-controller.yaml#
23 - enum:
[all …]
H A Dfsl,imx93-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx93-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX93 specific extensions to Synopsys Designware MIPI DSI
10 - Liu Ying <victor.liu@nxp.com>
13 There is a Synopsys Designware MIPI DSI Host Controller and a Synopsys
14 Designware MIPI DPHY embedded in Freescale i.MX93 SoC. Some configurations
15 and extensions to them are controlled by i.MX93 media blk-ctrl.
18 - $ref: snps,dw-mipi-dsi.yaml#
[all …]
H A Dlontium,lt9211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge.
10 - Marek Vasut <marex@denx.de>
13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
19 - lontium,lt9211
27 reset-gpios:
31 vccio-supply:
[all …]
H A Dchipone,icn6211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
10 - Jagan Teki <jagan@amarulasolutions.com>
13 ICN6211 is MIPI-DSI to RGB Converter bridge from chipone.
15 It has a flexible configuration of MIPI DSI signal input and
21 - chipone,icn6211
25 description: virtual channel number of a DSI peripheral
27 clock-names:
[all …]
H A Dtoshiba,tc358762.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358762 MIPI DSI to MIPI DPI bridge
10 - Marek Vasut <marex@denx.de>
13 The TC358762 is bridge device which converts MIPI DSI to MIPI DPI.
18 - toshiba,tc358762
22 description: virtual channel number of a DSI peripheral
24 reset-gpios:
27 vddc-supply:
[all …]
H A Dti,dlpc3433.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI DLPC3433 MIPI DSI to DMD bridge
10 - Jagan Teki <jagan@amarulasolutions.com>
11 - Christopher Vollo <chris@renewoutreach.org>
14 TI DLPC3433 is a MIPI DSI based display controller bridge
17 It has a flexible configuration of MIPI DSI and DPI signal
30 - 0x1b
31 - 0x1d
[all …]
H A Dsnps,dw-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare MIPI DSI host controller
10 - Philippe CORNU <philippe.cornu@foss.st.com>
13 This document defines device tree properties for the Synopsys DesignWare MIPI
14 DSI host controller. It doesn't constitute a device tree binding specification
15 by itself but is meant to be referenced by platform-specific device tree
23 - $ref: ../dsi-controller.yaml#
[all …]
H A Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
23 - ti,sn65dsi83
[all …]
H A Dnwl-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
10 - Guido Gúnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com>
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmixel,mipi-dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mixel DSI PHY for i.MX8
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
15 electrical signals for DSI.
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
[all …]
H A Dmediatek,dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek MIPI Display Serial Interface (DSI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 description: The MIPI DSI PHY supports up to 4-lane output.
19 pattern: "^dsi-phy@[0-9a-f]+$"
[all …]
/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra114-mipi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra MIPI pad calibration controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^mipi@[0-9a-f]+$"
19 - nvidia,tegra114-mipi
20 - nvidia,tegra124-mipi
[all …]
H A Dnvidia,tegra20-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
[all …]
H A Dnvidia,tegra20-csi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Svyatoslav Ryhel <clamor95@gmail.com>
15 - nvidia,tegra20-csi
16 - nvidia,tegra30-csi
24 - description: module clock
25 - description: PAD A clock
26 - description: PAD B clock
[all …]
/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mm-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
20 - const: fsl,imx8mm-disp-blk-ctrl
21 - const: syscon
[all …]
H A Dfsl,imx8mn-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MN DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
20 - const: fsl,imx8mn-disp-blk-ctrl
21 - const: syscon
[all …]
/linux/include/video/
H A Dmipi_display.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Defines for Mobile Industry Processor Interface (MIPI(R))
4 * Display Working Group standards: DSI, DCS, DBI, DPI
13 /* MIPI DSI Processor-to-Peripheral transaction types */
66 /* MIPI DSI Peripheral-to-Processor transaction types */
78 /* MIPI DCS commands */
111 MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */
128 MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */
129 MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */
130 MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */
[all …]
/linux/drivers/gpu/drm/tegra/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
30 #include "dsi.h"
31 #include "mipi-phy.h"
74 struct tegra_mipi_device *mipi; member
82 /* for ganged-mode support */
103 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
105 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
108 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
110 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
112 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
[all …]
/linux/Documentation/devicetree/bindings/display/panel/
H A Dorisetech,otm8009a.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Orise Tech OTM8009A 3.97" 480x800 TFT LCD panel (MIPI-DSI video mode)
10 - Philippe CORNU <philippe.cornu@foss.st.com>
14 a MIPI-DSI video interface. Its backlight is managed through the DSI link.
16 - $ref: panel-common.yaml#
25 description: DSI virtual channel
27 enable-gpios: true
29 power-supply: true
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun6i_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
11 #include <linux/crc-ccitt.h>
14 #include <linux/phy/phy-mipi-dphy.h>
291 static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi) in sun6i_dsi_inst_abort() argument
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
297 static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi) in sun6i_dsi_inst_commit() argument
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
304 static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi) in sun6i_dsi_inst_wait_for_completion() argument
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
[all …]
/linux/drivers/gpu/host1x/
H A Dmipi.c131 struct tegra_mipi *mipi; member
136 static inline u32 tegra_mipi_readl(struct tegra_mipi *mipi, in tegra_mipi_readl() argument
139 return readl(mipi->regs + (offset << 2)); in tegra_mipi_readl()
142 static inline void tegra_mipi_writel(struct tegra_mipi *mipi, u32 value, in tegra_mipi_writel() argument
145 writel(value, mipi->regs + (offset << 2)); in tegra_mipi_writel()
148 static int tegra_mipi_power_up(struct tegra_mipi *mipi) in tegra_mipi_power_up() argument
153 err = clk_enable(mipi->clk); in tegra_mipi_power_up()
157 value = tegra_mipi_readl(mipi, MIPI_CAL_BIAS_PAD_CFG0); in tegra_mipi_power_up()
160 if (mipi->soc->needs_vclamp_ref) in tegra_mipi_power_up()
163 tegra_mipi_writel(mipi, value, MIPI_CAL_BIAS_PAD_CFG0); in tegra_mipi_power_up()
[all …]

1234567