/linux/Documentation/devicetree/bindings/display/rockchip/ |
H A D | rockchip,dw-mipi-dsi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip specific extensions to the Synopsys Designware MIPI DSI 10 - Sandy Huang <hjc@rock-chips.com> 11 - Heiko Stuebner <heiko@sntech.de> 16 - enum: 17 - rockchip,px30-mipi-dsi 18 - rockchip,rk3128-mipi-dsi [all …]
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/linux/Documentation/devicetree/bindings/display/ |
H A D | allwinner,sun6i-a31-mipi-dsi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner A31 MIPI-DSI Controller 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 16 - enum: 17 - allwinner,sun6i-a31-mipi-dsi 18 - allwinner,sun50i-a64-mipi-dsi [all …]
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H A D | amlogic,meson-g12a-dw-mipi-dsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/display/amlogic,meson-g12a-dw-mipi-dsi.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller 11 - Neil Armstrong <neil.armstrong@linaro.org> 15 - A Synopsys DesignWare MIPI DSI Host Controller IP 16 - A TOP control block controlling the Clocks & Resets of the IP 19 - $ref: dsi-controller.yaml# 24 - amlogic,meson-g12a-dw-mipi-dsi [all …]
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/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | samsung,mipi-dsim.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Samsung MIPI DSIM bridge controller 10 - Inki Dae <inki.dae@samsung.com> 11 - Jagan Teki <jagan@amarulasolutions.com> 12 - Marek Szyprowski <m.szyprowski@samsung.com> 15 Samsung MIPI DSIM bridge controller can be found it on Exynos 21 - enum: [all …]
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H A D | intel,keembay-dsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/intel,keembay-dsi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Intel Keem Bay mipi dsi controller 10 - Anitha Chrisanthus <anitha.chrisanthus@intel.com> 11 - Edmond J Dea <edmund.j.dea@intel.com> 15 const: intel,keembay-dsi 19 - description: MIPI registers range 21 reg-names: [all …]
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H A D | renesas,dsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas RZ/G2L MIPI DSI Encoder 10 - Biju Das <biju.das.jz@bp.renesas.com> 13 This binding describes the MIPI DSI encoder embedded in the Renesas 14 RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with 18 - $ref: /schemas/display/dsi-controller.yaml# 23 - enum: [all …]
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H A D | fsl,imx93-mipi-dsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx93-mipi-dsi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Freescale i.MX93 specific extensions to Synopsys Designware MIPI DSI 10 - Liu Ying <victor.liu@nxp.com> 13 There is a Synopsys Designware MIPI DSI Host Controller and a Synopsys 14 Designware MIPI DPHY embedded in Freescale i.MX93 SoC. Some configurations 15 and extensions to them are controlled by i.MX93 media blk-ctrl. 18 - $ref: snps,dw-mipi-dsi.yaml# [all …]
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H A D | lontium,lt9211.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge. 10 - Marek Vasut <marex@denx.de> 13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS 14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI. 19 - lontium,lt9211 27 reset-gpios: 31 vccio-supply: [all …]
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H A D | chipone,icn6211.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge 10 - Jagan Teki <jagan@amarulasolutions.com> 13 ICN6211 is MIPI-DSI to RGB Converter bridge from chipone. 15 It has a flexible configuration of MIPI DSI signal input and 21 - chipone,icn6211 25 description: virtual channel number of a DSI peripheral 27 clock-names: [all …]
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H A D | toshiba,tc358762.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Toshiba TC358762 MIPI DSI to MIPI DPI bridge 10 - Marek Vasut <marex@denx.de> 13 The TC358762 is bridge device which converts MIPI DSI to MIPI DPI. 18 - toshiba,tc358762 22 description: virtual channel number of a DSI peripheral 24 reset-gpios: 27 vddc-supply: [all …]
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H A D | ti,sn65dsi83.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip 10 - Marek Vasut <marex@denx.de> 13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI 14 to 1x Single-link LVDS 16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI 17 to 1x Dual-link or 2x Single-link LVDS 23 - ti,sn65dsi83 [all …]
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H A D | ti,dlpc3433.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: TI DLPC3433 MIPI DSI to DMD bridge 10 - Jagan Teki <jagan@amarulasolutions.com> 11 - Christopher Vollo <chris@renewoutreach.org> 14 TI DLPC3433 is a MIPI DSI based display controller bridge 17 It has a flexible configuration of MIPI DSI and DPI signal 30 - 0x1b 31 - 0x1d [all …]
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H A D | snps,dw-mipi-dsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Synopsys DesignWare MIPI DSI host controller 10 - Philippe CORNU <philippe.cornu@foss.st.com> 13 This document defines device tree properties for the Synopsys DesignWare MIPI 14 DSI host controller. It doesn't constitute a device tree binding specification 15 by itself but is meant to be referenced by platform-specific device tree 23 - $ref: ../dsi-controller.yaml# [all …]
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H A D | nwl-dsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs 10 - Guido Gúnther <agx@sigxcpu.org> 11 - Robert Chiras <robert.chiras@nxp.com> 14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for 15 the SOCs NWL MIPI-DSI host controller. 18 - $ref: ../dsi-controller.yaml# [all …]
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H A D | renesas,dsi-csi2-tx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/renesas,dsi-csi2-tx.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas R-Car MIPI DSI/CSI-2 Encoder 10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> 13 This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas 14 R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up 20 - renesas,r8a779a0-dsi-csi2-tx # for V3U 21 - renesas,r8a779g0-dsi-csi2-tx # for V4H [all …]
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/linux/drivers/gpu/drm/bridge/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 21 Simple transparent bridge that is used by several non-DRM drivers to 36 tristate "Chipone ICN6211 MIPI-DSI/RGB Converter bridge" 43 ICN6211 is MIPI-DSI/RGB Converter bridge from chipone. 45 It has a flexible configuration of MIPI DSI signal input 67 ChromeOS EC ANX7688 is an ultra-low power 68 4K Ultra-HD (4096x2160p60) mobile HD transmitter 70 2.0 to DisplayPort 1.3 Ultra-HD. It is connected 77 Driver for display connectors with support for DDC and hot-plug 81 on ARM-based platforms. Saying Y here when this driver is not needed [all …]
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/linux/drivers/gpu/drm/exynos/ |
H A D | exynos_drm_dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Samsung MIPI DSIM glue for Exynos SoCs. 14 #include <drm/bridge/samsung-dsim.h> 27 struct exynos_dsi *dsi = dsim->priv; in exynos_dsi_te_irq_handler() local 28 struct drm_encoder *encoder = &dsi->encoder; in exynos_dsi_te_irq_handler() 30 if (dsim->state & DSIM_STATE_VIDOUT_AVAILABLE) in exynos_dsi_te_irq_handler() 31 exynos_drm_crtc_te_handler(encoder->crtc); in exynos_dsi_te_irq_handler() 39 struct exynos_dsi *dsi = dsim->priv; in exynos_dsi_host_attach() local 40 struct drm_encoder *encoder = &dsi->encoder; in exynos_dsi_host_attach() 41 struct drm_device *drm = encoder->dev; in exynos_dsi_host_attach() [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | mediatek,dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: MediaTek MIPI Display Serial Interface (DSI) PHY 11 - Chun-Kuang Hu <chunkuang.hu@kernel.org> 12 - Philipp Zabel <p.zabel@pengutronix.de> 13 - Chunfeng Yun <chunfeng.yun@mediatek.com> 15 description: The MIPI DSI PHY supports up to 4-lane output. 19 pattern: "^dsi-phy@[0-9a-f]+$" [all …]
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H A D | mixel,mipi-dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Mixel DSI PHY for i.MX8 10 - Guido Günther <agx@sigxcpu.org> 13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the 14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the 15 electrical signals for DSI. 18 in either MIPI-DSI PHY mode or LVDS PHY mode. [all …]
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/linux/Documentation/devicetree/bindings/display/tegra/ |
H A D | nvidia,tegra114-mipi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-mipi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra MIPI pad calibration controller 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 15 pattern: "^mipi@[0-9a-f]+$" 19 - nvidia,tegra114-mipi 20 - nvidia,tegra210-mipi [all …]
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H A D | nvidia,tegra20-dsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 16 - enum: 17 - nvidia,tegra20-dsi 18 - nvidia,tegra30-dsi 19 - nvidia,tegra114-dsi [all …]
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/linux/Documentation/devicetree/bindings/soc/imx/ |
H A D | fsl,imx8mm-disp-blk-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX8MM DISP blk-ctrl 10 - Lucas Stach <l.stach@pengutronix.de> 13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to 14 the NoC and ensuring proper power sequencing of the display and MIPI CSI 20 - const: fsl,imx8mm-disp-blk-ctrl 21 - const: syscon [all …]
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H A D | fsl,imx8mn-disp-blk-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX8MN DISP blk-ctrl 10 - Lucas Stach <l.stach@pengutronix.de> 13 The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to 14 the NoC and ensuring proper power sequencing of the display and MIPI CSI 20 - const: fsl,imx8mn-disp-blk-ctrl 21 - const: syscon [all …]
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/linux/include/video/ |
H A D | mipi_display.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Defines for Mobile Industry Processor Interface (MIPI(R)) 4 * Display Working Group standards: DSI, DCS, DBI, DPI 13 /* MIPI DSI Processor-to-Peripheral transaction types */ 66 /* MIPI DSI Peripheral-to-Processor transaction types */ 78 /* MIPI DCS commands */ 111 MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */ 128 MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */ 129 MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */ 130 MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */ [all …]
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/linux/drivers/gpu/drm/tegra/ |
H A D | dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only 29 #include "dsi.h" 30 #include "mipi-phy.h" 73 struct tegra_mipi_device *mipi; member 81 /* for ganged-mode support */ 102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument 104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state() 107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument 109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl() 111 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl() [all …]
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