1*e7dc9c3aSSvyatoslav Ryhel# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*e7dc9c3aSSvyatoslav Ryhel%YAML 1.2 3*e7dc9c3aSSvyatoslav Ryhel--- 4*e7dc9c3aSSvyatoslav Ryhel$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml# 5*e7dc9c3aSSvyatoslav Ryhel$schema: http://devicetree.org/meta-schemas/core.yaml# 6*e7dc9c3aSSvyatoslav Ryhel 7*e7dc9c3aSSvyatoslav Ryheltitle: NVIDIA Tegra20 CSI controller 8*e7dc9c3aSSvyatoslav Ryhel 9*e7dc9c3aSSvyatoslav Ryhelmaintainers: 10*e7dc9c3aSSvyatoslav Ryhel - Svyatoslav Ryhel <clamor95@gmail.com> 11*e7dc9c3aSSvyatoslav Ryhel 12*e7dc9c3aSSvyatoslav Ryhelproperties: 13*e7dc9c3aSSvyatoslav Ryhel compatible: 14*e7dc9c3aSSvyatoslav Ryhel enum: 15*e7dc9c3aSSvyatoslav Ryhel - nvidia,tegra20-csi 16*e7dc9c3aSSvyatoslav Ryhel - nvidia,tegra30-csi 17*e7dc9c3aSSvyatoslav Ryhel 18*e7dc9c3aSSvyatoslav Ryhel reg: 19*e7dc9c3aSSvyatoslav Ryhel maxItems: 1 20*e7dc9c3aSSvyatoslav Ryhel 21*e7dc9c3aSSvyatoslav Ryhel clocks: 22*e7dc9c3aSSvyatoslav Ryhel minItems: 1 23*e7dc9c3aSSvyatoslav Ryhel items: 24*e7dc9c3aSSvyatoslav Ryhel - description: module clock 25*e7dc9c3aSSvyatoslav Ryhel - description: PAD A clock 26*e7dc9c3aSSvyatoslav Ryhel - description: PAD B clock 27*e7dc9c3aSSvyatoslav Ryhel 28*e7dc9c3aSSvyatoslav Ryhel clock-names: 29*e7dc9c3aSSvyatoslav Ryhel items: 30*e7dc9c3aSSvyatoslav Ryhel - const: csi 31*e7dc9c3aSSvyatoslav Ryhel - const: csia-pad 32*e7dc9c3aSSvyatoslav Ryhel - const: csib-pad 33*e7dc9c3aSSvyatoslav Ryhel 34*e7dc9c3aSSvyatoslav Ryhel avdd-dsi-csi-supply: 35*e7dc9c3aSSvyatoslav Ryhel description: DSI/CSI power supply. Must supply 1.2 V. 36*e7dc9c3aSSvyatoslav Ryhel 37*e7dc9c3aSSvyatoslav Ryhel power-domains: 38*e7dc9c3aSSvyatoslav Ryhel maxItems: 1 39*e7dc9c3aSSvyatoslav Ryhel 40*e7dc9c3aSSvyatoslav Ryhel "#nvidia,mipi-calibrate-cells": 41*e7dc9c3aSSvyatoslav Ryhel description: 42*e7dc9c3aSSvyatoslav Ryhel The number of cells in a MIPI calibration specifier. Should be 1. 43*e7dc9c3aSSvyatoslav Ryhel The single cell specifies an id of the pad that need to be 44*e7dc9c3aSSvyatoslav Ryhel calibrated for a given device. Valid pad ids for receiver would be 45*e7dc9c3aSSvyatoslav Ryhel 0 for CSI-A; 1 for CSI-B; 2 for DSI-A and 3 for DSI-B. 46*e7dc9c3aSSvyatoslav Ryhel $ref: /schemas/types.yaml#/definitions/uint32 47*e7dc9c3aSSvyatoslav Ryhel const: 1 48*e7dc9c3aSSvyatoslav Ryhel 49*e7dc9c3aSSvyatoslav Ryhel "#address-cells": 50*e7dc9c3aSSvyatoslav Ryhel const: 1 51*e7dc9c3aSSvyatoslav Ryhel 52*e7dc9c3aSSvyatoslav Ryhel "#size-cells": 53*e7dc9c3aSSvyatoslav Ryhel const: 0 54*e7dc9c3aSSvyatoslav Ryhel 55*e7dc9c3aSSvyatoslav RyhelpatternProperties: 56*e7dc9c3aSSvyatoslav Ryhel "^channel@[0-1]$": 57*e7dc9c3aSSvyatoslav Ryhel type: object 58*e7dc9c3aSSvyatoslav Ryhel description: channel 0 represents CSI-A and 1 represents CSI-B 59*e7dc9c3aSSvyatoslav Ryhel additionalProperties: false 60*e7dc9c3aSSvyatoslav Ryhel 61*e7dc9c3aSSvyatoslav Ryhel properties: 62*e7dc9c3aSSvyatoslav Ryhel reg: 63*e7dc9c3aSSvyatoslav Ryhel maximum: 1 64*e7dc9c3aSSvyatoslav Ryhel 65*e7dc9c3aSSvyatoslav Ryhel nvidia,mipi-calibrate: 66*e7dc9c3aSSvyatoslav Ryhel description: Should contain a phandle and a specifier specifying 67*e7dc9c3aSSvyatoslav Ryhel which pad is used by this CSI channel and needs to be calibrated. 68*e7dc9c3aSSvyatoslav Ryhel $ref: /schemas/types.yaml#/definitions/phandle-array 69*e7dc9c3aSSvyatoslav Ryhel 70*e7dc9c3aSSvyatoslav Ryhel "#address-cells": 71*e7dc9c3aSSvyatoslav Ryhel const: 1 72*e7dc9c3aSSvyatoslav Ryhel 73*e7dc9c3aSSvyatoslav Ryhel "#size-cells": 74*e7dc9c3aSSvyatoslav Ryhel const: 0 75*e7dc9c3aSSvyatoslav Ryhel 76*e7dc9c3aSSvyatoslav Ryhel port@0: 77*e7dc9c3aSSvyatoslav Ryhel $ref: /schemas/graph.yaml#/$defs/port-base 78*e7dc9c3aSSvyatoslav Ryhel unevaluatedProperties: false 79*e7dc9c3aSSvyatoslav Ryhel description: port receiving the video stream from the sensor 80*e7dc9c3aSSvyatoslav Ryhel 81*e7dc9c3aSSvyatoslav Ryhel properties: 82*e7dc9c3aSSvyatoslav Ryhel endpoint: 83*e7dc9c3aSSvyatoslav Ryhel $ref: /schemas/media/video-interfaces.yaml# 84*e7dc9c3aSSvyatoslav Ryhel unevaluatedProperties: false 85*e7dc9c3aSSvyatoslav Ryhel 86*e7dc9c3aSSvyatoslav Ryhel required: 87*e7dc9c3aSSvyatoslav Ryhel - data-lanes 88*e7dc9c3aSSvyatoslav Ryhel 89*e7dc9c3aSSvyatoslav Ryhel port@1: 90*e7dc9c3aSSvyatoslav Ryhel $ref: /schemas/graph.yaml#/properties/port 91*e7dc9c3aSSvyatoslav Ryhel description: port sending the video stream to the VI 92*e7dc9c3aSSvyatoslav Ryhel 93*e7dc9c3aSSvyatoslav Ryhel required: 94*e7dc9c3aSSvyatoslav Ryhel - reg 95*e7dc9c3aSSvyatoslav Ryhel - "#address-cells" 96*e7dc9c3aSSvyatoslav Ryhel - "#size-cells" 97*e7dc9c3aSSvyatoslav Ryhel - port@0 98*e7dc9c3aSSvyatoslav Ryhel - port@1 99*e7dc9c3aSSvyatoslav Ryhel 100*e7dc9c3aSSvyatoslav RyhelallOf: 101*e7dc9c3aSSvyatoslav Ryhel - if: 102*e7dc9c3aSSvyatoslav Ryhel properties: 103*e7dc9c3aSSvyatoslav Ryhel compatible: 104*e7dc9c3aSSvyatoslav Ryhel contains: 105*e7dc9c3aSSvyatoslav Ryhel enum: 106*e7dc9c3aSSvyatoslav Ryhel - nvidia,tegra20-csi 107*e7dc9c3aSSvyatoslav Ryhel then: 108*e7dc9c3aSSvyatoslav Ryhel properties: 109*e7dc9c3aSSvyatoslav Ryhel clocks: 110*e7dc9c3aSSvyatoslav Ryhel maxItems: 1 111*e7dc9c3aSSvyatoslav Ryhel 112*e7dc9c3aSSvyatoslav Ryhel clock-names: false 113*e7dc9c3aSSvyatoslav Ryhel 114*e7dc9c3aSSvyatoslav Ryhel - if: 115*e7dc9c3aSSvyatoslav Ryhel properties: 116*e7dc9c3aSSvyatoslav Ryhel compatible: 117*e7dc9c3aSSvyatoslav Ryhel contains: 118*e7dc9c3aSSvyatoslav Ryhel enum: 119*e7dc9c3aSSvyatoslav Ryhel - nvidia,tegra30-csi 120*e7dc9c3aSSvyatoslav Ryhel then: 121*e7dc9c3aSSvyatoslav Ryhel properties: 122*e7dc9c3aSSvyatoslav Ryhel clocks: 123*e7dc9c3aSSvyatoslav Ryhel minItems: 3 124*e7dc9c3aSSvyatoslav Ryhel 125*e7dc9c3aSSvyatoslav Ryhel clock-names: 126*e7dc9c3aSSvyatoslav Ryhel minItems: 3 127*e7dc9c3aSSvyatoslav Ryhel 128*e7dc9c3aSSvyatoslav RyheladditionalProperties: false 129*e7dc9c3aSSvyatoslav Ryhel 130*e7dc9c3aSSvyatoslav Ryhelrequired: 131*e7dc9c3aSSvyatoslav Ryhel - compatible 132*e7dc9c3aSSvyatoslav Ryhel - reg 133*e7dc9c3aSSvyatoslav Ryhel - clocks 134*e7dc9c3aSSvyatoslav Ryhel - power-domains 135*e7dc9c3aSSvyatoslav Ryhel - "#address-cells" 136*e7dc9c3aSSvyatoslav Ryhel - "#size-cells" 137*e7dc9c3aSSvyatoslav Ryhel 138*e7dc9c3aSSvyatoslav Ryhel# see nvidia,tegra20-vi.yaml for an example 139