| /linux/drivers/net/mdio/ |
| H A D | Kconfig | 3 # MDIO Layer Configuration
7 tristate "MDIO bus consumer layer"
9 MDIO bus consumer layer
17 FWNODE MDIO bus (Ethernet PHY) accessors
23 OpenFirmware MDIO bus (Ethernet PHY) accessors
28 ACPI MDIO bus (Ethernet PHY) accessors
31 tristate "Airoha AN7583 MDIO bus controller"
34 This module provides a driver for the MDIO busses found in the
38 tristate "Allwinner sun4i MDIO interface support"
41 This driver supports the MDIO interface found in the network
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| H A D | Makefile | 2 # Makefile for Linux MDIO bus drivers
8 obj-$(CONFIG_MDIO_AIROHA) += mdio-airoha.o
9 obj-$(CONFIG_MDIO_ASPEED) += mdio-aspeed.o
10 obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o
11 obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o
12 obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
13 obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium.o
14 obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
15 obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
16 obj-$(CONFIG_MDIO_I2C) += mdio-i2c.o
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| H A D | mdio-mvusb.c | 27 struct mii_bus *mdio; member
32 static int mvusb_mdio_read(struct mii_bus *mdio, int dev, int reg) in mvusb_mdio_read() argument
34 struct mvusb_mdio *mvusb = mdio->priv; in mvusb_mdio_read()
52 static int mvusb_mdio_write(struct mii_bus *mdio, int dev, int reg, u16 val) in mvusb_mdio_write() argument
54 struct mvusb_mdio *mvusb = mdio->priv; in mvusb_mdio_write()
69 struct mii_bus *mdio; in mvusb_mdio_probe() local
72 mdio = devm_mdiobus_alloc_size(dev, sizeof(*mvusb)); in mvusb_mdio_probe()
73 if (!mdio) in mvusb_mdio_probe()
76 mvusb = mdio->priv; in mvusb_mdio_probe()
77 mvusb->mdio = mdio; in mvusb_mdio_probe()
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| H A D | acpi_mdio.c | 3 * ACPI helpers for the MDIO (Ethernet PHY) API
19 MODULE_DESCRIPTION("ACPI MDIO bus (Ethernet PHY) accessors");
23 * @mdio: pointer to mii_bus structure
24 * @fwnode: pointer to fwnode of MDIO bus. This fwnode is expected to represent
25 * @owner: module owning this @mdio object.
26 * an ACPI device object corresponding to the MDIO bus and its children are
32 int __acpi_mdiobus_register(struct mii_bus *mdio, struct fwnode_handle *fwnode, in __acpi_mdiobus_register() argument
40 mdio->phy_mask = GENMASK(31, 0); in __acpi_mdiobus_register()
41 ret = __mdiobus_register(mdio, owner); in __acpi_mdiobus_register()
45 ACPI_COMPANION_SET(&mdio->dev, to_acpi_device_node(fwnode)); in __acpi_mdiobus_register()
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| /linux/Documentation/devicetree/bindings/net/ |
| H A D | fsl,fman-mdio.yaml | 4 $id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
7 title: Freescale Frame Manager MDIO Device
12 description: FMan MDIO Node.
13 The MDIO is a bus to which the PHY devices are connected.
18 - fsl,fman-mdio
20 - fsl,fman-memac-mdio
22 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
23 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
24 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
38 fsl,fman-internal-mdio:
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| H A D | allwinner,sun8i-a83t-emac.yaml | 129 mdio-mux:
135 const: allwinner,sun8i-h3-mdio-mux
137 mdio-parent-bus:
140 Phandle to EMAC MDIO.
148 mdio@1:
149 $ref: mdio.yaml#
151 description: Internal MDIO Bus
155 const: allwinner,sun8i-h3-mdio-internal
180 mdio@2:
181 $ref: mdio.yaml#
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| H A D | qcom,ipq4019-mdio.yaml | 4 $id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml#
7 title: Qualcomm IPQ40xx MDIO Controller
16 - qcom,ipq4019-mdio
17 - qcom,ipq5018-mdio
21 - qcom,ipq6018-mdio
22 - qcom,ipq8074-mdio
23 - qcom,ipq9574-mdio
24 - const: qcom,ipq4019-mdio
36 the first Address and length of the register set for the MDIO controller.
42 - description: MDIO clock source frequency fixed to 100MHZ
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| H A D | fsl,cpm-mdio.yaml | 4 $id: http://devicetree.org/schemas/net/fsl,cpm-mdio.yaml#
7 title: Freescale CPM MDIO Device
16 - fsl,pq1-fec-mdio
17 - fsl,cpm2-mdio-bitbang
19 - const: fsl,mpc8272ads-mdio-bitbang
20 - const: fsl,mpc8272-mdio-bitbang
21 - const: fsl,cpm2-mdio-bitbang
26 fsl,mdio-pin:
28 description: pin of port C controlling mdio data
32 description: pin of port C controlling mdio clock
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| H A D | cavium-mdio.txt | 1 * System Management Interface (SMI) / MDIO
6 "cavium,octeon-3860-mdio": Compatibility with all cn3XXX, cn5XXX
9 "cavium,thunder-8890-mdio": Compatibility with all cn8XXX SOCs.
11 - reg: The base address of the MDIO bus controller register bank.
15 - #size-cells: Must be <0>. MDIO addresses have no size component.
17 Typically an MDIO bus might have several children.
20 mdio@1180000001800 {
21 compatible = "cavium,octeon-3860-mdio";
33 * System Management Interface (SMI) / MDIO Nexus
35 Several mdio buses may be gathered as children of a single PCI
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| H A D | fsl,gianfar-mdio.yaml | 4 $id: http://devicetree.org/schemas/net/fsl,gianfar-mdio.yaml#
7 title: Freescale Gianfar (TSEC) MDIO Device
10 This binding describes the MDIO is a bus to which the PHY devices are
15 PHY is accessed through the local MDIO bus. These buses are defined similarly
16 to the mdio buses, except they are compatible with "fsl,gianfar-tbi". The TBI
24 # This is needed to distinguish gianfar.yaml and gianfar-mdio.yaml, because
33 const: mdio
42 - fsl,gianfar-mdio
44 - fsl,etsec2-mdio
45 - fsl,ucc-mdio
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| H A D | mdio-mux-multiplexer.yaml | 4 $id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
7 title: Properties for an MDIO bus multiplexer consumer device
13 This is a special case of MDIO mux when MDIO mux is defined as a consumer
19 - $ref: /schemas/net/mdio-mux.yaml#
23 const: mdio-mux-multiplexer
43 mdio-mux-1 { // Mux consumer
44 compatible = "mdio-mux-multiplexer";
46 mdio-parent-bus = <&emdio1>;
50 mdio@0 {
56 mdio@8 {
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| H A D | realtek,rtl9301-mdio.yaml | 4 $id: http://devicetree.org/schemas/net/realtek,rtl9301-mdio.yaml#
7 title: Realtek RTL9300 MDIO Controller
17 - realtek,rtl9302b-mdio
18 - realtek,rtl9302c-mdio
19 - realtek,rtl9303-mdio
20 - const: realtek,rtl9301-mdio
21 - const: realtek,rtl9301-mdio
33 '^mdio-bus@[0-3]$':
34 $ref: mdio.yaml#
59 mdio-controller@ca00 {
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| H A D | hisilicon-hns-mdio.txt | 1 Hisilicon MDIO bus controller
5 "hisilicon,hns-mdio"
6 "hisilicon,mdio"
7 "hisilicon,hns-mdio" is recommended to be used for hip05 and later SOCs,
8 while "hisilicon,mdio" is optional for backwards compatibility only on
10 - reg: The base address of the MDIO bus controller register bank.
12 - #size-cells: Must be <0>. MDIO addresses have no size component.
14 Typically an MDIO bus might have several children.
17 mdio@803c0000 {
20 compatible = "hisilicon,hns-mdio","hisilicon,mdio";
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| H A D | mdio-mux-mmioreg.yaml | 4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
19 - $ref: /schemas/net/mdio-mux.yaml#
24 - const: mdio-mux-mmioreg
25 - const: mdio-mux
37 child mdio-mux node must be constrained by this mask.
48 mdio-mux@9 {
49 compatible = "mdio-mux-mmioreg", "mdio-mux";
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| H A D | amlogic,gxl-mdio-mux.yaml | 4 $id: http://devicetree.org/schemas/net/amlogic,gxl-mdio-mux.yaml#
7 title: Amlogic GXL MDIO bus multiplexer
13 This is a special case of a MDIO bus multiplexer. It allows to choose between
14 the internal mdio bus leading to the embedded 10/100 PHY or the external
15 MDIO bus on the Amlogic GXL SoC family.
18 - $ref: mdio-mux.yaml#
22 const: amlogic,gxl-mdio-mux
44 eth_phy_mux: mdio@558 {
45 compatible = "amlogic,gxl-mdio-mux";
51 mdio-parent-bus = <&mdio0>;
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| H A D | amlogic,g12a-mdio-mux.yaml | 4 $id: http://devicetree.org/schemas/net/amlogic,g12a-mdio-mux.yaml#
7 title: MDIO bus multiplexer/glue of Amlogic G12a SoC family
10 This is a special case of a MDIO bus multiplexer. It allows to choose between
11 the internal mdio bus leading to the embedded 10/100 PHY or the external
12 MDIO bus.
18 - $ref: mdio-mux.yaml#
22 const: amlogic,g12a-mdio-mux
51 mdio-multiplexer@4c000 {
52 compatible = "amlogic,g12a-mdio-mux";
56 mdio-parent-bus = <&mdio0>;
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| H A D | mdio.yaml | 4 $id: http://devicetree.org/schemas/net/mdio.yaml#
7 title: MDIO Bus Common Properties
15 These are generic properties that can apply to any MDIO bus. Any
16 MDIO bus must have a list of child nodes, one per device on the
22 pattern: '^mdio(-(bus|external))?(@.+|-([0-9]+))?$'
34 lines of all devices on that MDIO bus.
38 RESET pulse width in microseconds. It applies to all MDIO devices
44 Delay after reset deassert in microseconds. It applies to all MDIO
51 Desired MDIO bus clock frequency in Hz. Values greater than IEEE 802.3
75 If set, indicates the MDIO device does not correctly release
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| H A D | apm-xgene-mdio.txt | 1 APM X-Gene SoC MDIO node
3 MDIO node is defined to describe on-chip MDIO controller.
6 - compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi"
12 For the phys on the mdio bus, there must be a node with the following fields:
18 mdio: mdio@17020000 {
19 compatible = "apm,xgene-mdio-rgmii";
27 &mdio {
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| H A D | mdio-gpio.yaml | 4 $id: http://devicetree.org/schemas/net/mdio-gpio.yaml#
7 title: MDIO on GPIOs
15 - $ref: mdio.yaml#
20 - virtual,mdio-gpio
21 - microchip,mdio-smi0
33 - description: MDIO
36 # Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases"
44 mdio-gpio0 = &mdio0;
47 mdio0: mdio {
48 compatible = "virtual,mdio-gpio";
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| /linux/drivers/net/pcs/ |
| H A D | pcs-lynx.c | 3 * Lynx PCS MDIO helpers
6 #include <linux/mdio.h>
25 struct mdio_device *mdio; member
112 phylink_mii_c22_pcs_get_state(lynx->mdio, neg_mode, state); in lynx_pcs_get_state()
115 lynx_pcs_get_state_2500basex(lynx->mdio, state); in lynx_pcs_get_state()
118 lynx_pcs_get_state_usxgmii(lynx->mdio, state); in lynx_pcs_get_state()
121 phylink_mii_c45_pcs_get_state(lynx->mdio, state); in lynx_pcs_get_state()
127 dev_dbg(&lynx->mdio->dev, in lynx_pcs_get_state()
201 return lynx_pcs_config_giga(lynx->mdio, ifmode, advertising, in lynx_pcs_config()
205 dev_err(&lynx->mdio->dev, in lynx_pcs_config()
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | fsl-lx2162a-qds.dts | 33 mdio-mux-1 {
34 compatible = "mdio-mux-multiplexer";
36 mdio-parent-bus = <&emdio1>;
40 mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */
52 mdio@8 { /* On-board RTL8211F PHY #2 RGMII2 */
64 mdio@18 { /* Slot #1 */
70 mdio@19 { /* Slot #2 */
76 mdio@1a { /* Slot #3 */
82 mdio@1b { /* Slot #4 */
88 mdio@1c { /* Slot #5 */
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| H A D | fsl-lx2160a-qds.dts | 35 mdio-mux-1 {
36 compatible = "mdio-mux-multiplexer";
38 mdio-parent-bus = <&emdio1>;
42 mdio@0 { /* On-board PHY #1 RGMI1*/
53 mdio@8 { /* On-board PHY #2 RGMI2*/
64 mdio@18 { /* Slot #1 */
70 mdio@19 { /* Slot #2 */
76 mdio@1a { /* Slot #3 */
82 mdio@1b { /* Slot #4 */
88 mdio@1c { /* Slot #5 */
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| /linux/drivers/net/ethernet/xilinx/ |
| H A D | xilinx_axienet_mdio.c | 3 * MDIO bus driver for the Xilinx Axi Ethernet device
24 * axienet_mdio_wait_until_ready - MDIO wait function
29 * Wait till MDIO interface is ready to accept a new transaction.
41 * axienet_mdio_mdc_enable - MDIO MDC enable function
44 * Enable the MDIO MDC. Called prior to a read/write operation
53 * axienet_mdio_mdc_disable - MDIO MDC disable function
56 * Disable the MDIO MDC. Called after a read/write operation
68 * axienet_mdio_read - MDIO interface read function
117 * axienet_mdio_write - MDIO interface write function
165 * axienet_mdio_enable - MDIO hardware setup function
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| /linux/drivers/net/ethernet/hisilicon/ |
| H A D | hns_mdio.c | 38 u8 __iomem *vbase; /* mdio reg base address */
43 /* mdio reg */
210 * @bus: mdio bus
226 dev_dbg(&bus->dev, "mdio write %s,base is %p\n", in hns_mdio_write_c22()
234 dev_err(&bus->dev, "MDIO bus is busy\n"); in hns_mdio_write_c22()
251 * @bus: mdio bus
268 dev_dbg(&bus->dev, "mdio write %s,base is %p\n", in hns_mdio_write_c45()
276 dev_err(&bus->dev, "MDIO bus is busy\n"); in hns_mdio_write_c45()
289 dev_err(&bus->dev, "MDIO bus is busy\n"); in hns_mdio_write_c45()
307 * @bus: mdio bus
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| /linux/drivers/net/ethernet/freescale/ |
| H A D | fsl_pq_mdio.c | 52 u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/
53 u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/
55 u32 emapm; /* MDIO Event mapping register (for etsec2)*/
91 * to the local interface, which may be different from the generic mdio bus
95 * mdio pins, which may not be the same as system mdio bus, used for
126 * may be different from the generic mdio bus. This is helpful in programming
128 * SERDES and are always tied to the local mdio pins, which may not be the
129 * same as system mdio bus, used for controlling the external PHYs, for eg.
198 * of the mapped GFAR MDIO registers (struct gfar)
230 * Return the TBIPAR address for a QE MDIO node, starting from the address
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