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/linux/drivers/net/ethernet/intel/igb/
H A De1000_phy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
31 * igb_check_reset_block - Check if PHY reset is blocked
48 * igb_get_phy_id - Retrieve the PHY ID and revision
56 struct e1000_phy_info *phy = &hw->phy; in igb_get_phy_id()
61 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) in igb_get_phy_id()
62 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0); in igb_get_phy_id()
64 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igb_get_phy_id()
68 phy->id = (u32)(phy_id << 16); in igb_get_phy_id()
70 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igb_get_phy_id()
[all …]
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
271 /* 1000/H is not supported, nor spec-compliant. */
309 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
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H A Digb_ethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
104 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
106 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
130 "legacy-rx",
139 struct e1000_hw *hw = &adapter->hw; in igb_get_link_ksettings()
140 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; in igb_get_link_ksettings()
141 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; in igb_get_link_ksettings()
146 status = pm_runtime_suspended(&adapter->pdev->dev) ? in igb_get_link_ksettings()
148 if (hw->phy.media_type == e1000_media_type_copper) { in igb_get_link_ksettings()
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H A De1000_mac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
19 * igb_get_bus_info_pcie - Get PCIe bus information
28 struct e1000_bus_info *bus = &hw->bus; in igb_get_bus_info_pcie()
33 bus->type = e1000_bus_type_pci_express; in igb_get_bus_info_pcie()
39 bus->width = e1000_bus_width_unknown; in igb_get_bus_info_pcie()
40 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
44 bus->speed = e1000_bus_speed_2500; in igb_get_bus_info_pcie()
47 bus->speed = e1000_bus_speed_5000; in igb_get_bus_info_pcie()
50 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Dphy.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
99 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
104 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
158 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */
201 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */
216 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
217 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
37 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
54 * e1000e_get_phy_id - Retrieve the PHY ID and revision
62 struct e1000_phy_info *phy = &hw->phy; in e1000e_get_phy_id()
67 if (!phy->ops.read_reg) in e1000e_get_phy_id()
75 phy->id = (u32)(phy_id << 16); in e1000e_get_phy_id()
81 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in e1000e_get_phy_id()
82 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); in e1000e_get_phy_id()
84 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) in e1000e_get_phy_id()
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H A D80003es2lan.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
35 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
40 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_80003es2lan()
43 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_80003es2lan()
44 phy->type = e1000_phy_none; in e1000_init_phy_params_80003es2lan()
47 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_80003es2lan()
48 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; in e1000_init_phy_params_80003es2lan()
51 phy->addr = 1; in e1000_init_phy_params_80003es2lan()
52 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_80003es2lan()
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H A Dethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
28 "s0ix-enabled",
36 .sizeof_stat = sizeof(((struct e1000_adapter *)0)->m), \
41 .sizeof_stat = sizeof(((struct rtnl_link_stats64 *)0)->m), \
115 struct e1000_hw *hw = &adapter->hw; in e1000_get_link_ksettings()
117 if (hw->phy.media_type == e1000_media_type_copper) { in e1000_get_link_ksettings()
127 if (hw->phy.type == e1000_phy_ife) in e1000_get_link_ksettings()
131 if (hw->mac.autoneg == 1) { in e1000_get_link_ksettings()
134 advertising |= hw->phy.autoneg_advertised; in e1000_get_link_ksettings()
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H A Ddefines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
238 /* 1000/H is not supported, nor spec-compliant. */
292 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
504 /* Loop limit on how long we wait for auto-negotiation to complete */
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/linux/Documentation/devicetree/bindings/net/pse-pd/
H A Dpse-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/pse-pd/pse-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 power over twisted pair/ethernet cable. The ethernet-pse nodes should be
12 used to describe PSE controller and referenced by the ethernet-phy node.
15 - Oleksij Rempel <o.rempel@pengutronix.de>
16 - Kory Maincent <kory.maincent@bootlin.com>
20 pattern: "^ethernet-pse(@.*|-([0-9]|[1-9][0-9]+))?$"
22 "#pse-cells":
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/linux/Documentation/networking/pse-pd/
H A Dpse-pi.rst1 .. SPDX-License-Identifier: GPL-2.0
9 eight-pin modular jack, commonly known as the Ethernet RJ45 port. This
14 ---------------------------
19 - Section "33.2.3 PI pin assignments" covers the pin assignments for PoE
21 - Section "145.2.4 PSE PI" addresses the configuration for PoE systems that
25 -------------------------------
31 two pairs of wires, SPE operates on a simpler model due to its single-pair
33 assignments for power delivery, as described in the PSE PI for multi-pair
37 --------------------
47 ----------------------------
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/linux/Documentation/devicetree/bindings/net/
H A Dqcom,qca807x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Robert Marko <robert.marko@sartura.hr>
15 IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and
16 1000BASE-T PHY-s.
21 Both models have a combo port that supports 1000BASE-X and
22 100BASE-FX fiber.
25 output only pins that natively drive LED-s for up to 2 attached
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/linux/drivers/net/ethernet/intel/igc/
H A Digc_phy.c1 // SPDX-License-Identifier: GPL-2.0
8 * igc_check_reset_block - Check if PHY reset is blocked
26 * igc_get_phy_id - Retrieve the PHY ID and revision
34 struct igc_phy_info *phy = &hw->phy; in igc_get_phy_id()
38 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igc_get_phy_id()
42 phy->id = (u32)(phy_id << 16); in igc_get_phy_id()
44 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igc_get_phy_id()
48 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in igc_get_phy_id()
49 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); in igc_get_phy_id()
56 * igc_phy_has_link - Polls PHY for link
[all …]
/linux/drivers/net/ethernet/atheros/atlx/
H A Datlx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* atlx_hw.h -- common hardware definitions for Attansic network drivers
4 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
5 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
6 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
10 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
149 /* IRQ Anti-Lost Timer Initial Value Register */
228 /* MAC Half-Duplex Control Register */
246 /* Wake-On-Lan control register */
331 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
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/linux/drivers/net/ethernet/intel/e1000/
H A De1000_param.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
12 #define OPTION_UNSET -1
22 #define E1000_PARAM(X, desc) \ argument
23 static int X[E1000_MAX_NIC+1] = E1000_PARAM_INIT; \
24 static unsigned int num_##X; \
25 module_param_array_named(X, X, int, &num_##X, 0); \
26 MODULE_PARM_DESC(X, desc);
30 * Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
31 * Valid Range: 80-4096 for 82544 and newer
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H A De1000_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
422 /* MAC decode size is 128K - This is the size of BAR0 */
443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
486 * E1000_RAR_ENTRIES - 1 multicast addresses.
503 /* Receive Descriptor - Extended */
529 /* Receive Descriptor - Packet Split */
553 __le16 length[3]; /* length of buffers 1-3 */
567 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
770 * RW - register is both readable and writable
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/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dvsc8211.c2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
53 VSC_INTR_DESCRAMBL = 1 << 7, /* descrambler lock-lost */
77 #define V_ACSR_ACTIPHY_TMR(x) ((x) << S_ACSR_ACTIPHY_TMR) argument
81 #define G_ACSR_SPEED(x) (((x) >> S_ACSR_SPEED) & M_ACSR_SPEED) argument
134 int err, sp = -1, dplx = -1, pause = 0; in vsc8211_get_link_status()
144 * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it in vsc8211_get_link_status()
210 int err, sp = -1, dplx = -1, pause = 0; in vsc8211_get_link_status_fiber()
220 * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it in vsc8211_get_link_status_fiber()
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/linux/include/uapi/linux/
H A Dethtool.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
26 * have the same layout for 32-bit and 64-bit userland.
38 * struct ethtool_cmd - DEPRECATED, link control and status
43 * interface supports autonegotiation or auto-detection.
44 * Read-onl
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/linux/drivers/platform/mellanox/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
38 Centers (EDC) for building Ethernet based clusters, High-Performance
49 This driver handles hot-plug events for the power suppliers, power
69 This driver provides support for the Mellanox MSN4800-XX line cards,
72 Centers (EDC) for building Ethernet based clusters, High-Performance
116 L3 management switches. It has 48 x 1Gbps RJ45 + 4 x 100G QSFP28
118 serial port (RS-232 interface), an OOB port (1G/100M MDI interface)
122 System equipped with Nvidia®Spectrum-1 32x100GbE Ethernet switch.
/linux/drivers/net/phy/
H A Dsmsc.c1 // SPDX-License-Identifier: GPL-2.0+
27 /* Vendor-specific PHY Definitions */
70 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in smsc_phy_config_intr()
91 struct smsc_phy_priv *priv = phydev->priv; in smsc_phy_config_edpd()
93 if (priv->edpd_enable) in smsc_phy_config_edpd()
107 if (irq_status != -ENODEV) in smsc_phy_handle_interrupt()
124 struct smsc_phy_priv *priv = phydev->priv; in smsc_phy_config_init()
130 if (!priv->edpd_mode_set_by_user && phydev->irq != PHY_POLL) in smsc_phy_config_init()
131 priv->edpd_enable = false; in smsc_phy_config_init()
162 /* When auto-negotiation is disabled (forced mode), the PHY's in lan87xx_config_aneg()
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H A Dmicrochip.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <dt-bindings/net/microchip-lan78xx.h>
42 struct lan88xx_priv *priv = phydev->priv; in lan88xx_suspend()
45 if (!priv->wolopts) in lan88xx_suspend()
94 phydev_warn(phydev, "TR Register[0x%X] configuration failed\n", in lan88xx_TR_reg_set()
105 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf, in lan88xx_config_TR_regs()
113 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv, in lan88xx_config_TR_regs()
121 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh in lan88xx_config_TR_regs()
129 * Write 24-bit value 0xEEFFDD to register. Setting in lan88xx_config_TR_regs()
138 * Write 24-bit value 0x071448 to register. Setting in lan88xx_config_TR_regs()
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/linux/arch/m68k/include/asm/
H A Dfbio.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #define FBTYPE_NOTYPE -1
83 int emu_type; /* -1 if none */
174 int mdi_ncluts; /* Number of implemented CLUTs in this MDI */
183 /* SparcLinux specific ioctl for the MDI, should be replaced for
258 #define CG14_XLUT 0x3000 /* X Look Up Table -- ??? */
/linux/drivers/net/ethernet/atheros/atl1e/
H A Datl1e_hw.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
200 /* IRQ Anti-Lost Timer Initial Value Register */
206 #define IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC i…
207 #define IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC i…
208 #define IDLE_STATUS_RXQ 4 /* 1: RXQ state machine is in non-IDLE state. 0: RXQ is …
209 #define IDLE_STATUS_TXQ 8 /* 1: TXQ state machine is in non-IDLE state. 0: TXQ is …
210 #define IDLE_STATUS_DMAR 0x10 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is…
211 #define IDLE_STATUS_DMAW 0x20 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is…
212 #define IDLE_STATUS_SMB 0x40 /* 1: SMB state machine is in non-IDLE state. 0: SMB is …
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/linux/drivers/video/fbdev/
H A Dcg14.c1 // SPDX-License-Identifier: GPL-2.0-only
138 u16 cursx; /* Cursor x,y position */
139 u16 cursy; /* Cursor x,y position */
167 * colors) for each MDI page (I assume then there should be 4 MDI
203 struct cg14_regs __iomem *regs = par->regs; in __cg14_reset()
206 val = sbus_readb(&regs->mcr); in __cg14_reset()
208 sbus_writeb(val, &regs->mcr); in __cg14_reset()
213 struct cg14_par *par = (struct cg14_par *) info->par; in cg14_pan_display()
219 spin_lock_irqsave(&par->lock, flags); in cg14_pan_display()
221 spin_unlock_irqrestore(&par->lock, flags); in cg14_pan_display()
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/linux/arch/powerpc/platforms/85xx/
H A Dmpc85xx_mds.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
10 * Yin Olivia <Hong-hua.Yin@freescale.com>
39 #include <asm/pci-bridge.h>
131 /* Disable automatic MDI/MDIX selection */ in mpc8568_mds_phy_fixups()
189 * U-Boot mangles interrupt polarity for Marvell PHYs, in mpc85xx_mds_reset_ucc_phys()
190 * so reset built-in and UEM Marvell PHYs, this puts in mpc85xx_mds_reset_ucc_phys()
203 prop = of_get_property(np, "cell-index", NULL); in mpc85xx_mds_reset_ucc_phys()
207 ucc_num = *prop - 1; in mpc85xx_mds_reset_ucc_phys()
209 prop = of_get_property(np, "phy-connection-type", NULL); in mpc85xx_mds_reset_ucc_phys()
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