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/linux/Documentation/devicetree/bindings/iommu/
H A Dmediatek,iommu.yaml13 Some MediaTek SOCs contain a Multimedia Memory Management Unit (M4U), and
14 this M4U have two generations of HW architecture. Generation one uses flat
18 About the M4U Hardware Block Diagram, please check below:
22 m4u (Multimedia Memory Management Unit)
52 As above, The Multimedia HW will go through SMI and M4U while it
53 access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain
55 HW should go through the m4u for translation or bypass it and talk
65 smi-common and m4u, and additional GALS module between smi-larb and
73 - mediatek,mt2701-m4u # generation one
74 - mediatek,mt2712-m4u # generation two
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/linux/include/dt-bindings/memory/
H A Dmt2701-larb-port.h11 * Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers,
15 * But m4u generation 2 like mt8173 have different port number, it use fixed
/linux/drivers/iommu/
H A DKconfig334 Support for the M4U on certain Mediatek SOCs. M4U is MultiMedia
341 tristate "MediaTek IOMMU Version 1 (M4U gen1) Support"
348 Support for the M4U on certain Mediatek SoCs. M4U generation 1 HW is
H A Dmtk_iommu.c318 * In M4U 4GB mode, the physical address is remapped as below:
334 * The Region 'A'(I/O) can NOT be mapped by M4U; For Region 'B'/'C'/'D', the
343 static LIST_HEAD(m4ulist); /* List all the M4U HWs */
379 /* If 2 M4U share a domain(use the same hwlist), Put the corresponding info in first data.*/
755 if (!bank->m4u_dom) { /* Initialize the M4U HW for each a BANK */ in mtk_iommu_attach_device()
817 /* The "4GB mode" M4U physically can not use the lower remap of Dram. */ in mtk_iommu_map()
1014 /* Get the m4u device */ in mtk_iommu_of_xlate()
1903 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1904 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1905 { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data},
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H A Dmtk_iommu_v1.c3 * IOMMU API for MTK architected m4u v1 implementations
94 * MTK m4u support 4GB iova address space, and only support 4K page
435 /* Get the m4u device */ in mtk_iommu_v1_create_mapping()
599 { .compatible = "mediatek,mt2701-m4u", },
779 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations");
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8167.dtsi172 iommu: m4u@10203000 {
173 compatible = "mediatek,mt8167-m4u";
H A Dmt2712e.dtsi327 compatible = "mediatek,mt2712-m4u";
345 compatible = "mediatek,mt2712-m4u";
H A Dmt8192.dtsi1649 iommu0: m4u@1401d000 {
1650 compatible = "mediatek,mt8192-m4u";
H A Dmt8365.dtsi532 compatible = "mediatek,mt8365-m4u";
H A Dmt8173.dtsi585 compatible = "mediatek,mt8173-m4u";
H A Dmt8183.dtsi1057 compatible = "mediatek,mt8183-m4u";
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623n.dtsi104 compatible = "mediatek,mt7623-m4u",
105 "mediatek,mt2701-m4u";
H A Dmt2701.dtsi219 compatible = "mediatek,mt2701-m4u";
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmediatek,smi-larb.yaml71 hardware id is not consecutive from its M4U point of view.
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-infracfg.c37 GATE_MTK(CLK_INFRA_M4U, "m4u", "axi_sel", &infra_cg_regs, 8, &mtk_clk_gate_ops_setclr),
/linux/drivers/memory/
H A Dmtk-smi.c208 /* do not need to enable m4u for this port */ in mtk_smi_larb_config_port_gen1()
883 * m4u port, and we need to enable the aync clock for transform the smi in mtk_smi_common_probe()