Home
last modified time | relevance | path

Searched full:m2 (Results 1 – 25 of 222) sorted by relevance

123456789

/linux/arch/arm64/boot/dts/ti/
H A Dk3-am642-hummingboard-t.dts53 regulator-m2-3v3 {
57 regulator-name = "m2-3v3";
83 * - select: 0 = USB-3 (M2); 1 = PCIE (M1)
93 m2-reset-hog {
97 line-name = "m2-reset";
100 m1-m2-w-disable1-hog {
104 line-name = "m1-m2-pcie-w-disable1";
107 m1-m2-w-disable2-hog {
111 line-name = "m1-m2-pcie-w-disable2";
123 m2-pcie-clkreq-hog {
[all …]
H A Dk3-am6548-iot2050-advanced-m2.dts22 compatible = "siemens,iot2050-advanced-m2", "ti,am654";
23 model = "SIMATIC IOT2050 Advanced M2";
33 main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins {
40 main_m2_pcie_mux_control: main-m2-pcie-mux-control-default-pins {
50 main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins {
/linux/tools/testing/selftests/tc-testing/tc-tests/qdiscs/
H A Dhfsc.json38 … "matchPattern": "class hfsc 1:1 parent 1: sc m1 0bit d 0us m2 20Kbit ul m1 0bit d 0us m2 10Kbit",
60 …matchPattern": "class hfsc 1:1 parent 1: sc m1 2464Kbit d 5ms m2 10Kbit ul m1 0bit d 0us m2 10Kbit…
82 … "matchPattern": "class hfsc 1:1 parent 1: rt m1 0bit d 0us m2 20Kbit ls m1 0bit d 0us m2 10Kbit",
104 …matchPattern": "class hfsc 1:1 parent 1: rt m1 2464Kbit d 5ms m2 10Kbit ls m1 0bit d 0us m2 10Kbit…
167 … "matchPattern": "class hfsc 1:1 parent 1: sc m1 0bit d 0us m2 8bit.*rt m1 0bit d 0us m2 8bit",
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dpllnv04.c151 int M1, N1, M2, N2, log2P; in getMNP_double() local
177 for (M2 = minM2; M2 <= maxM2; M2++) { in getMNP_double()
178 if (calcclk1/M2 < minU2) in getMNP_double()
180 if (calcclk1/M2 > maxU2) in getMNP_double()
184 N2 = (clkP * M2 + calcclk1/2) / calcclk1; in getMNP_double()
192 if (N2/M2 < 4 || N2/M2 > 10) in getMNP_double()
195 calcclk2 = calcclk1 * N2 / M2; in getMNP_double()
214 *pM2 = M2; in getMNP_double()
228 int *N1, int *M1, int *N2, int *M2, int *P) in nv04_pll_calc() argument
236 *M2 = 1; in nv04_pll_calc()
[all …]
H A Dnv40.c62 int M2 = (coef & 0x00ff0000) >> 16; in read_pll_2() local
71 if (M2) in read_pll_2()
72 khz = khz * N2 / M2; in read_pll_2()
125 int *N1, int *M1, int *N2, int *M2, int *log2P) in nv40_clk_calc_pll() argument
138 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P); in nv40_clk_calc_pll()
151 int N1, M1, N2, M2, log2P; in nv40_clk_calc() local
156 &N1, &M1, &N2, &M2, &log2P); in nv40_clk_calc()
160 if (N2 == M2) { in nv40_clk_calc()
165 clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_clk_calc()
H A Dnv04.c35 int N1, M1, N2, M2, P; in nv04_clk_pll_calc() local
36 int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P); in nv04_clk_pll_calc()
42 pv->M2 = M2; in nv04_clk_pll_calc()
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_pll.c45 unsigned n, m, mf, m2, sd; in hdmi_pll_compute() local
59 /* adjust m2 so that the clkdco will be high enough */ in hdmi_pll_compute()
61 m2 = DIV_ROUND_UP(min_dco, target_bitclk); in hdmi_pll_compute()
62 if (m2 == 0) in hdmi_pll_compute()
63 m2 = 1; in hdmi_pll_compute()
65 target_clkdco = target_bitclk * m2; in hdmi_pll_compute()
79 clkout = clkdco / m2; in hdmi_pll_compute()
84 DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n", in hdmi_pll_compute()
85 n, m, mf, m2, sd); in hdmi_pll_compute()
91 pi->mX[0] = m2; in hdmi_pll_compute()
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5-bananapi-m2-plus.dts6 #include <arm/allwinner/sunxi-bananapi-m2-plus.dtsi>
9 model = "Banana Pi BPI-M2-Plus H5";
10 compatible = "sinovoip,bpi-m2-plus", "allwinner,sun50i-h5";
H A Dsun50i-h5-bananapi-m2-plus-v1.2.dts7 #include <arm/allwinner/sunxi-bananapi-m2-plus-v1.2.dtsi>
10 model = "Banana Pi BPI-M2-Plus v1.2 H5";
11 compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5";
/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-h3-bananapi-m2-plus-v1.2.dts8 #include "sunxi-bananapi-m2-plus-v1.2.dtsi"
11 model = "Banana Pi BPI-M2-Plus v1.2 H3";
12 compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun8i-h3";
H A Dsun8i-h3-bananapi-m2-plus.dts45 #include "sunxi-bananapi-m2-plus.dtsi"
48 model = "Banana Pi BPI-M2-Plus H3";
49 compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
H A Dsunxi-bananapi-m2-plus-v1.2.dtsi6 #include "sunxi-bananapi-m2-plus.dtsi"
10 * Bananapi M2+ v1.2 uses a GPIO line to change the effective
/linux/Documentation/i2c/
H A Di2c-topology.rst201 '--------' | | mux M1 |--. | mux M2 |--. .--------.
209 and specifically when M2 requests its parent to lock, M1 passes
212 This topology is bad if M2 is an auto-closing mux and M1->select
214 through and be seen by the M2 adapter, thus closing M2 prematurely.
225 '--------' | | mux M1 |--. | mux M2 |--. .--------.
248 '--------' | | mux M1 |--. | mux M2 |--. .--------.
260 be avoided. The reason is that M2 probably assumes that there will
262 if there are, any such transfers might appear on the slave side of M2
266 The topology is especially troublesome if M2 is an auto-closing
267 mux. In that case, any interleaved accesses to D4 might close M2
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_fw_defs.h20 IRO[157].m2))
23 IRO[158].m2))
29 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
32 * IRO[142].m2) + ((sbId) * IRO[142].m3))
39 (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
41 (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
43 (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
45 (IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2))
47 (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
49 (IRO[322].base + ((pfId) * IRO[322].m1) + ((iscsiEqId) * IRO[322].m2))
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-data-modul-edm-sbc.dts226 "", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#",
227 "WDOG_KICK#", "M2-B_PCIE_CLKREQ#",
237 "M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#",
240 "M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#",
252 "", "", "", "M2-B_WAKE_WWAN_1V8#",
253 "M2-B_RESET_1V8#", "", "", "",
708 /* M2-B_RESET_1V8# */
710 /* M2-B_PCIE_RST# */
712 /* M2-B_FULL_CARD_PWROFF_1V8# */
714 /* M2-B_W_DISABLE1_WWAN_1V8# */
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dpll.c270 * clkout = clkdco / m2
278 unsigned int n, m, mf, m2, sd; in dss_pll_calc_b() local
287 /* adjust m2 so that the clkdco will be high enough */ in dss_pll_calc_b()
289 m2 = DIV_ROUND_UP(min_dco, target_clkout); in dss_pll_calc_b()
290 if (m2 == 0) in dss_pll_calc_b()
291 m2 = 1; in dss_pll_calc_b()
293 target_clkdco = target_clkout * m2; in dss_pll_calc_b()
307 clkout = clkdco / m2; in dss_pll_calc_b()
312 DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n", in dss_pll_calc_b()
313 n, m, mf, m2, sd); in dss_pll_calc_b()
[all …]
/linux/tools/testing/selftests/powerpc/benchmarks/
H A Dcontext_switch.c319 static unsigned long *m1, *m2; variable
326 m2 = &_m2; in futex_setup()
347 m2 = shmaddr + sizeof(*m1); in futex_setup()
351 *m2 = 0; in futex_setup()
354 mutex_lock(m2); in futex_setup()
363 mutex_lock(m2); in futex_thread1()
375 mutex_unlock(m2); in futex_thread2()
/linux/drivers/clk/meson/
H A Dclk-dualdiv.h17 unsigned int m2; member
25 struct parm m2; member
/linux/include/dt-bindings/power/
H A Dr8a7793-sysc.h13 * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains.
/linux/drivers/gpu/drm/gma500/
H A Dgma_display.c727 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in gma_pll_is_valid()
728 GMA_PLL_INVALID("m2 out of range"); in gma_pll_is_valid()
732 if (clock->m1 <= clock->m2 && clock->m1 != 0) in gma_pll_is_valid()
733 GMA_PLL_INVALID("m1 <= m2 && m1 != 0"); in gma_pll_is_valid()
784 for (clock.m2 = limit->m2.min; in gma_find_best_pll()
785 (clock.m2 < clock.m1 || clock.m1 == 0) && in gma_find_best_pll()
786 clock.m2 <= limit->m2.max; clock.m2++) { in gma_find_best_pll()
H A Dcdv_intel_display.c43 .m2 = {.min = 58, .max = 158},
55 .m2 = {.min = 58, .max = 158},
70 .m2 = {.min = 65, .max = 130},
82 .m2 = {.min = 58, .max = 158},
94 .m2 = {.min = 65, .max = 130},
106 .m2 = {.min = 58, .max = 162},
273 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
396 clock->m = clock->m2 + 2; in cdv_intel_clock()
419 clock.m2 = 118; in cdv_intel_find_dp_pll()
425 clock.m2 = 98; in cdv_intel_find_dp_pll()
[all …]
/linux/tools/perf/pmu-events/arch/test/test_soc/cpu/
H A Dmetrics.json49 "MetricExpr": "ipc + M2",
54 "MetricName": "M2"
/linux/Documentation/hwmon/
H A Dibmaem.rst11 This includes the x3350, x3550, x3650, x3655, x3755, x3850 M2,
12 x3950 M2, and certain HC10/HS2x/LS2x/QS2x blades.
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c210 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */ in setPLL_double_highregs()
217 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4; in setPLL_double_highregs()
296 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; in setPLL_double_lowregs()
363 int N1, M1, N2, M2, P; in nv04_devinit_pll_set() local
370 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv04_devinit_pll_set()
378 pv.M2 = M2; in nv04_devinit_pll_set()
/linux/Documentation/devicetree/bindings/power/
H A Drenesas,apmu.yaml27 - renesas,r8a7791-apmu # R-Car M2-W
29 - renesas,r8a7793-apmu # R-Car M2-N

123456789