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/linux/drivers/char/tpm/
H A Dtpm_tis_spi_main.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Christophe Ricard <christophe-h.ricard@st.com>
10 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
47 * [1] https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
49 static int tpm_tis_spi_flow_control(struct tpm_tis_spi_phy *phy, in tpm_tis_spi_flow_control() argument
52 struct spi_message m; in tpm_tis_spi_flow_control() local
55 if ((phy->iobuf[3] & 0x01) == 0) { in tpm_tis_spi_flow_control()
58 spi_xfer->len = 1; in tpm_tis_spi_flow_control()
59 spi_message_init(&m); in tpm_tis_spi_flow_control()
60 spi_message_add_tail(spi_xfer, &m); in tpm_tis_spi_flow_control()
[all …]
H A Dtpm_tis_spi_cr50.c1 // SPDX-License-Identifier: GPL-2.0
23 * - can go to sleep not earlier than after CR50_SLEEP_DELAY_MSEC.
24 * - needs up to CR50_WAKE_START_DELAY_USEC to wake after sleep.
25 * - requires waiting for "ready" IRQ, if supported; or waiting for at least
27 * - waits for up to CR50_FLOW_CONTROL for flow control 'ready' indication.
55 static inline struct cr50_spi_phy *to_cr50_spi_phy(struct tpm_tis_spi_phy *phy) in to_cr50_spi_phy() argument
57 return container_of(phy, struct cr50_spi_phy, spi_phy); in to_cr50_spi_phy()
69 cr50_phy->irq_confirmed = true; in cr50_spi_irq_handler()
70 complete(&cr50_phy->spi_phy.ready); in cr50_spi_irq_handler()
79 static void cr50_ensure_access_delay(struct cr50_spi_phy *phy) in cr50_ensure_access_delay() argument
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/linux/drivers/staging/greybus/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
11 To compile this code as a module, chose M here: the module
12 will be called gb-audio.ko
20 bridge from an APB-I2S port to a Unipro network.
22 To compile this code as a module, chose M here: the module
23 will be called gb-audio-codec.ko
32 To compile this code as a module, chose M here: the module
33 will be called gb-bootrom.ko
42 To compile this code as a module, chose M here: the module
43 will be called gb-camera.ko
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek Universal Flash Storage (UFS) M-PHY
11 - Stanley Chu <stanley.chu@mediatek.com>
12 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
16 Each UFS M-PHY node should have its own node.
17 To bind UFS M-PHY with UFS host controller, the controller node should
[all …]
H A Dstarfive,jh7110-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 USB 2.0 PHY
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-usb-phy
19 "#phy-cells":
24 - description: PHY 125m
25 - description: app 125m
[all …]
H A Drockchip,inno-usb2phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip USB2.0 phy with inno IP block
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
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H A Drockchip,rk3288-dp-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip specific extensions to the Analogix Display Port PHY
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3288-dp-phy
19 clock-names:
20 const: 24m
22 "#phy-cells":
[all …]
/linux/drivers/usb/phy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
26 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, this can't be 'y'
32 tristate "Keystone USB PHY Driver"
36 Enable this to support Keystone USB phy. This driver provides
37 interface to interact with USB 2.0 and USB 3.0 PHY that is part
42 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, NOP can't be built-in
46 built-in with usb ip or which are autonomous and doesn't require any
47 phy programming such as ISP1x04 etc.
53 tristate "AM335x USB PHY Driver"
60 This driver provides PHY support for that phy which part for the
[all …]
/linux/drivers/phy/starfive/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for StarFive platforms
9 tristate "StarFive JH7110 D-PHY RX support"
14 Choose this option if you have a StarFive D-PHY in your
15 system. If M is selected, the module will be called
16 phy-jh7110-dphy-rx.ko.
19 tristate "StarFive JH7110 D-PHY TX Support"
24 Choose this option if you have a StarFive D-PHY TX in your
25 system. If M is selected, the module will be called
26 phy-jh7110-dphy-tx.ko.
[all …]
H A Dphy-jh7110-usb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 USB 2.0 PHY driver
15 #include <linux/phy/phy.h>
28 struct phy *phy; member
36 static void usb2_set_ls_keepalive(struct jh7110_usb2_phy *phy, bool set) in usb2_set_ls_keepalive() argument
40 /* Host mode enable the LS speed keep-alive signal */ in usb2_set_ls_keepalive()
41 val = readl(phy->regs + USB_LS_KEEPALIVE_OFF); in usb2_set_ls_keepalive()
47 writel(val, phy->regs + USB_LS_KEEPALIVE_OFF); in usb2_set_ls_keepalive()
50 static int usb2_phy_set_mode(struct phy *_phy, in usb2_phy_set_mode()
53 struct jh7110_usb2_phy *phy = phy_get_drvdata(_phy); in usb2_phy_set_mode() local
[all …]
/linux/drivers/phy/marvell/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Marvell platforms
6 bool "Armada 375 USB cluster PHY support" if COMPILE_TEST
12 tristate "Marvell Berlin SATA PHY driver"
17 Enable this to support the SATA PHY on Marvell Berlin SoCs.
20 tristate "Marvell Berlin USB PHY Driver"
25 Enable this to support the USB PHY on Marvell Berlin SoCs.
46 Enable this to support Marvell A3700 UTMI PHY driver.
76 Enable this to support Marvell CP110 UTMI PHY driver.
85 tristate "Marvell USB HSIC 28nm PHY Driver"
[all …]
/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-lvds-phy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2020,2022 NXP
12 #include <linux/phy/phy.h>
23 #define M(n) FIELD_PREP(M_MASK, (n)) macro
36 #define CTRL_RESET_VAL (M(0x0) | CCM(0x4) | CA(0x4) | TST(0x25))
38 /* PHY initialization value and mask */
40 #define CTRL_INIT_VAL (M(0x0) | CCM(0x5) | CA(0x4) | TST(0x25) | RFB)
54 struct phy *phy; member
66 static int mixel_lvds_phy_init(struct phy *phy) in mixel_lvds_phy_init() argument
68 struct mixel_lvds_phy_priv *priv = dev_get_drvdata(phy->dev.parent); in mixel_lvds_phy_init()
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/linux/drivers/phy/hisilicon/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Hisilicon platforms
6 tristate "hi6220 USB PHY support"
12 Enable this to support the HISILICON HI6220 USB PHY.
14 To compile this driver as a module, choose M here.
17 tristate "hi3660 USB PHY support"
22 Enable this to support the HISILICON HI3660 USB PHY.
24 To compile this driver as a module, choose M here.
27 tristate "hi3670 USB PHY support"
32 Enable this to support the HISILICON HI3670 USB PHY.
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_hdmi_phy_clk.c1 // SPDX-License-Identifier: GPL-2.0+
6 #include <linux/clk-provider.h>
12 struct sun8i_hdmi_phy *phy; member
23 unsigned long rate = req->rate; in sun8i_phy_clk_determine_rate()
49 abs(rate - rounded / i) < in sun8i_phy_clk_determine_rate()
50 abs(rate - best_rate / best_div)) { in sun8i_phy_clk_determine_rate()
61 req->rate = best_rate / best_div; in sun8i_phy_clk_determine_rate()
62 req->best_parent_rate = best_rate; in sun8i_phy_clk_determine_rate()
63 req->best_parent_hw = best_parent; in sun8i_phy_clk_determine_rate()
74 regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG, &reg); in sun8i_phy_clk_recalc_rate()
[all …]
/linux/drivers/net/fddi/skfp/
H A Dsmt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
26 #define m_fc(mb) ((mb)->sm_data[0])
55 static int phy_index(struct s_smc *smc, int phy);
57 static int phy_con_resource_index(struct s_smc *smc, int phy);
82 static void smt_fill_lem(struct s_smc *smc, struct smt_p_lem *lem, int phy);
111 return(*(short *)(&addr->a[0]) == in is_my_addr()
112 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[0]) in is_my_addr()
113 && *(short *)(&addr->a[2]) == in is_my_addr()
114 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[2]) in is_my_addr()
115 && *(short *)(&addr->a[4]) == in is_my_addr()
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Dcn9132-clearfog.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9132-sr-cex7.dtsi"
19 compatible = "solidrun,cn9132-clearfog",
20 "solidrun,cn9132-sr-cex7", "marvell,cn9130";
32 gpio-keys {
33 compatible = "gpio-keys";
[all …]
/linux/drivers/scsi/bfa/
H A Dbfa_ioc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
31 bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->ioc_timer, \
33 #define bfa_ioc_timer_stop(__ioc) bfa_timer_stop(&(__ioc)->ioc_timer)
36 bfa_timer_begin((__ioc)->timer_mod, &(__ioc)->hb_timer, \
38 #define bfa_hb_timer_stop(__ioc) bfa_timer_stop(&(__ioc)->hb_timer)
55 ((__ioc)->ioc_hwif->ioc_firmware_lock(__ioc))
57 ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc))
[all …]
/linux/drivers/phy/microchip/
H A Dlan966x_serdes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/phy.h>
8 #include <linux/phy/phy.h>
11 #include <dt-bindings/phy/phy-lan966x-serdes.h>
38 #define SERDES_MUX_GMII(i, p, m, c) \ argument
39 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_GMII, m, c)
40 #define SERDES_MUX_SGMII(i, p, m, c) \ argument
41 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_SGMII, m, c)
42 #define SERDES_MUX_QSGMII(i, p, m, c) \ argument
43 SERDES_MUX(i, p, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_QSGMII, m, c)
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
[all …]
/linux/drivers/phy/qualcomm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm eDP PHY driver"
28 Enable this driver to support the Qualcomm eDP PHY found in various
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-friendlyelec-cm3588-nas.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
14 #include <dt-bindings/usb/pd.h>
15 #include "rk3588-friendlyelec-cm3588.dtsi"
19 compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588";
21 adc_key_recovery: adc-key-recovery {
22 compatible = "adc-keys";
[all …]
/linux/drivers/phy/rockchip/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Rockchip platforms
6 tristate "Rockchip Display Port PHY Driver"
10 Enable this to support the Rockchip Display Port PHY.
21 To compile this driver as a module, choose M here: the module
22 will be called phy-rockchip-dphy-rx0.
25 tristate "Rockchip EMMC PHY Driver"
29 Enable this to support the Rockchip EMMC PHY.
32 tristate "Rockchip INNO HDMI PHY Driver"
38 Enable this to support the Rockchip Innosilicon HDMI PHY.
[all …]
/linux/drivers/gpu/drm/bridge/imx/
H A Dimx93-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/media-bus-format.h>
16 #include <linux/phy/phy.h>
17 #include <linux/phy/phy-mipi-dphy.h>
42 #define M(x) FIELD_PREP(M_MASK, ((x) - 2)) macro
44 #define N(x) FIELD_PREP(N_MASK, ((x) - 1))
106 u32 m; /* PLL Feedback Multiplication Ratio */ member
121 /* DPHY Databook Table 3-13 Charge-pump Programmability */
136 /* DPHY Databook Table 5-7 Frequency Ranges and Defaults */
207 ret = regmap_write(dsi->regmap, reg, value); in dphy_pll_write()
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c1 // SPDX-License-Identifier: MIT
36 } dot, vco, n, m, m1, m2, p, p1; member
47 .m = { .min = 96, .max = 140 },
60 .m = { .min = 96, .max = 140 },
73 .m = { .min = 96, .max = 140 },
86 .m = { .min = 70, .max = 120 },
99 .m = { .min = 70, .max = 120 },
113 .m = { .min = 104, .max = 138 },
128 .m = { .min = 104, .max = 138 },
141 .m = { .min = 104, .max = 138 },
[all …]
/linux/drivers/phy/intel/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # Phy drivers for Intel platforms
6 tristate "Intel Keem Bay EMMC PHY driver"
14 To compile this driver as a module, choose M here: the module
15 will be called phy-keembay-emmc.ko.
18 tristate "Intel Keem Bay USB PHY driver"
26 To compile this driver as a module, choose M here: the module
27 will be called phy-keembay-usb.ko.
44 tristate "Intel Lightning Mountain EMMC PHY driver"
48 Enable this to support the Intel EMMC PHY

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