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/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_kr.h154 * @param lane lane number
160 enum al_eth_an_lt_lane lane,
167 * @param lane lane number
173 enum al_eth_an_lt_lane lane,
180 * @param lane lane number
186 enum al_eth_an_lt_lane lane,
193 * @param lane lane number
199 enum al_eth_an_lt_lane lane,
206 * @param lane lane number
211 enum al_eth_an_lt_lane lane);
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H A Dal_hal_eth_kr.c212 enum al_eth_an_lt_lane lane) in al_eth_an_lt_reg_read() argument
218 al_assert(lane == AL_ETH_AN__LT_LANE_0); in al_eth_an_lt_reg_read()
233 switch (lane) { in al_eth_an_lt_reg_read()
275 al_err("%s: Unknown Lane %d\n", __func__, lane); in al_eth_an_lt_reg_read()
281 al_dbg("[%s]: %s - (%s) lane %d, reg %d, val 0x%x", adapter->name, __func__, in al_eth_an_lt_reg_read()
282 (an_lt == AL_ETH_AN_REGS) ? "AN" : "LT", lane, reg_addr, val); in al_eth_an_lt_reg_read()
291 enum al_eth_an_lt_lane lane, in al_eth_an_lt_reg_write() argument
310 switch (lane) { in al_eth_an_lt_reg_write()
356 al_err("%s: Unknown Lane %d\n", __func__, lane); in al_eth_an_lt_reg_write()
362 al_dbg("[%s]: %s - (%s) lane %d, reg %d, val 0x%x", adapter->name, __func__, in al_eth_an_lt_reg_write()
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H A Dal_hal_eth_mac_regs.h979 /* Lane alignment status */
981 /* Lane synchronization */
997 /* Lane alignment status */
999 /* Lane synchronization */
1115 * RXAUI Lane 0 Input
1124 * RXAUI Lane 1 Input
1133 * XAUI Lane 0 Input
1142 * XAUI Lane 1 Input
1151 * XAUI Lane 2 Input
1160 * XAUI Lane 3 Input
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PerfectShuffle.h29 2080972802U, // <0,0,0,1>: Cost 2 ins <0,0,u,1>, lane 2
31 2085707777U, // <0,0,0,3>: Cost 2 ins <0,u,0,3>, lane 1
33 2080440323U, // <0,0,0,5>: Cost 2 ins <0,0,0,u>, lane 3
34 2080440323U, // <0,0,0,6>: Cost 2 ins <0,0,0,u>, lane 3
35 2080440323U, // <0,0,0,7>: Cost 2 ins <0,0,0,u>, lane 3
40 2080514051U, // <0,0,1,3>: Cost 2 ins <0,0,1,u>, lane 3
42 2085797889U, // <0,0,1,5>: Cost 2 ins <0,u,1,5>, lane 1
43 2080514051U, // <0,0,1,6>: Cost 2 ins <0,0,1,u>, lane 3
44 2080514051U, // <0,0,1,7>: Cost 2 ins <0,0,1,u>, lane 3
49 1012113409U, // <0,0,2,3>: Cost 1 ins LHS, lane 1
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_25g.c281 enum al_serdes_lane lane, in al_serdes_25g_bist_rx_enable() argument
285 switch (lane) { in al_serdes_25g_bist_rx_enable()
320 al_err("%s: Wrong serdes lane %d\n", __func__, lane); in al_serdes_25g_bist_rx_enable()
326 (enum al_serdes_reg_page)lane, in al_serdes_25g_bist_rx_enable()
333 (enum al_serdes_reg_page)lane, in al_serdes_25g_bist_rx_enable()
340 (enum al_serdes_reg_page)lane, in al_serdes_25g_bist_rx_enable()
349 (enum al_serdes_reg_page)lane, in al_serdes_25g_bist_rx_enable()
357 (enum al_serdes_reg_page)lane, in al_serdes_25g_bist_rx_enable()
368 (enum al_serdes_reg_page)lane, in al_serdes_25g_bist_rx_enable()
376 // TODO: [Guy] change API to be per lane.
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H A Dal_hal_serdes_interface.h120 * Parallel loopback from the PMA receive lane data ports, to the
121 * transmit lane data ports
511 * SERDES lane Rx rate change software flow enable
514 * @param lane The SERDES lane within the group
518 * SERDES lane Rx rate change software flow disable
521 * @param lane The SERDES lane within the group
525 * PCIe lane rate override check
529 * @param lane The SERDES lane within the group
535 * PCIe lane rate override control
538 * @param lane The SERDES lane within the group
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H A Dal_hal_serdes_hssp.c111 * Lane Rx rate change software flow disable
115 enum al_serdes_lane lane);
124 * Lane Rx rate change software flow enable if all conditions met
128 enum al_serdes_lane lane);
508 enum al_serdes_lane lane) in al_serdes_lane_rx_rate_change_sw_flow_en() argument
510 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 201, 0xfc); in al_serdes_lane_rx_rate_change_sw_flow_en()
511 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 202, 0xff); in al_serdes_lane_rx_rate_change_sw_flow_en()
512 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 203, 0xff); in al_serdes_lane_rx_rate_change_sw_flow_en()
513 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 204, 0xff); in al_serdes_lane_rx_rate_change_sw_flow_en()
514 al_serdes_reg_write(obj, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA, 205, 0x7f); in al_serdes_lane_rx_rate_change_sw_flow_en()
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H A Dal_hal_serdes_hssp_internal_regs.h43 * Per lane register fields
46 * RX and TX lane hard reset
56 * RX and TX lane hard reset control
65 /* RX lane power state control */
74 /* TX lane power state control */
83 /* RX lane word width */
93 /* TX lane word width */
103 /* RX lane rate select */
111 /* TX lane rate select */
137 * RX pads). Serial IO loopback from the transmit lane IO pins to the receive
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H A Dal_hal_serdes_internal_regs.h44 * Per lane register fields
47 * RX and TX lane hard reset
57 * RX and TX lane hard reset control
66 /* RX lane power state control */
75 /* TX lane power state control */
84 /* RX lane word width */
94 /* TX lane word width */
104 /* RX lane rate select */
112 /* TX lane rate select */
138 * RX pads). Serial IO loopback from the transmit lane IO pins to the receive
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/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_xusbpadctl.c216 struct padctl_lane *lane; member
253 struct padctl_lane *lane);
255 struct padctl_lane *lane);
262 static int usb2_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
263 static int usb2_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
264 static int pcie_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
265 static int pcie_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
266 static int sata_powerup(struct padctl_softc *sc, struct padctl_lane *lane);
267 static int sata_powerdown(struct padctl_softc *sc, struct padctl_lane *lane);
304 #define LANE(n, p, r, s, m, mx) { \ macro
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/freebsd/sys/dev/drm2/
H A Ddrm_dp_helper.c43 int lane) in dp_get_lane_status() argument
45 int i = DP_LANE0_1_STATUS + (lane >> 1); in dp_get_lane_status()
46 int s = (lane & 1) * 4; in dp_get_lane_status()
56 int lane; in drm_dp_channel_eq_ok() local
62 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
63 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_channel_eq_ok()
74 int lane; in drm_dp_clock_recovery_ok() local
77 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
78 lane_status = dp_get_lane_status(link_status, lane); in drm_dp_clock_recovery_ok()
87 int lane) in drm_dp_get_adjust_request_voltage() argument
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/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_xusbpadctl.c378 struct padctl_lane *lane; member
416 struct padctl_lane *lane);
418 struct padctl_lane *lane);
427 static int usb2_enable(struct padctl_softc *sc, struct padctl_lane *lane);
428 static int usb2_disable(struct padctl_softc *sc, struct padctl_lane *lane);
429 static int hsic_enable(struct padctl_softc *sc, struct padctl_lane *lane);
430 static int hsic_disable(struct padctl_softc *sc, struct padctl_lane *lane);
431 static int pcie_enable(struct padctl_softc *sc, struct padctl_lane *lane);
432 static int pcie_disable(struct padctl_softc *sc, struct padctl_lane *lane);
433 static int sata_enable(struct padctl_softc *sc, struct padctl_lane *lane);
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Donnn,nb7vpq904m.yaml54 An array of physical data lane indexes. Position determines how
57 Lane number represents the following
58 - 0 is RX2 lane
59 - 1 is TX2 lane
60 - 2 is TX1 lane
61 - 3 is RX1 lane
72 - Port A to RX2 lane
73 - Port B to TX2 lane
74 - Port C to TX1 lane
75 - Port D to RX1 lane
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/freebsd/sys/arm64/rockchip/
H A Drk_typec_phy.c84 #define TX_TXCC_MGNFS_MULT_000(lane) ((0x4050 | ((lane) << 9)) << 2) argument
85 #define XCVR_DIAG_BIDI_CTRL(lane) ((0x40e8 | ((lane) << 9)) << 2) argument
86 #define XCVR_DIAG_LANE_FCM_EN_MGN(lane) ((0x40f2 | ((lane) << 9)) << 2) argument
87 #define TX_PSC_A0(lane) ((0x4100 | ((lane) << 9)) << 2) argument
88 #define TX_PSC_A1(lane) ((0x4101 | ((lane) << 9)) << 2) argument
89 #define TX_PSC_A2(lane) ((0x4102 | ((lane) << 9)) << 2) argument
90 #define TX_PSC_A3(lane) ((0x4103 | ((lane) << 9)) << 2) argument
91 #define TX_RCVDET_EN_TMR(lane) ((0x4122 | ((lane) << 9)) << 2) argument
92 #define TX_RCVDET_ST_TMR(lane) ((0x4123 | ((lane) << 9)) << 2) argument
94 #define RX_PSC_A0(lane) ((0x8000 | ((lane) << 9)) << 2) argument
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dvideo-interfaces.yaml165 # Assume up to 9 physical lane indices
168 An array of physical data lane indexes. Position of an entry determines
169 the logical lane number, while the value of an entry indicates physical
170 lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
171 assuming the clock lane is on hardware lane 0. If the hardware does not
172 support lane reordering, monotonically incremented values shall be used
174 lane. This property is valid for serial busses only (e.g. MIPI CSI-2).
178 # Assume up to 9 physical lane indice
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/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dst,st-mipid02.yaml17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
18 second input port is a single lane 800Mbps. Both ports support clock
19 and data lane polarity swap. First port also supports data lane swap.
65 Single-lane operation shall be <1> or <2> .
66 Dual-lane operation shall be <1 2> or <2 1> .
70 lane-polarities:
72 Any lane can be inverted or not.
91 Single-lane operatio
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H A Dst,st-mipid02.txt6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7 input port is a single lane 800Mbps. Both ports support clock and data lane
8 polarity swap. First port also supports data lane swap.
37 - data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be
38 <1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
40 - lane-polarities: any lane can be inverted or not.
/freebsd/contrib/arm-optimized-routines/math/aarch64/
H A Dv_pow.c14 for (int lane = 0; lane < v_lanes64 (); lane++) in V_NAME_D2() local
16 double sx = x[lane]; in V_NAME_D2()
17 double sy = y[lane]; in V_NAME_D2()
19 z[lane] = sz; in V_NAME_D2()
H A Dv_powf.c106 for (int lane = 0; lane < 4; lane++) in V_NAME_F2() local
108 /* Use double precision for each lane. */ in V_NAME_F2()
109 double invc = data.log2_tab[i[lane]].invc; in V_NAME_F2()
110 double logc = data.log2_tab[i[lane]].logc; in V_NAME_F2()
111 double z = (double) asfloat (iz[lane]); in V_NAME_F2()
115 double y0 = logc + (double) k[lane]; in V_NAME_F2()
123 double ylogx = y[lane] * logx; in V_NAME_F2()
124 cmp[lane] = (asuint64 (ylogx) >> 47 & 0xffff) in V_NAME_F2()
127 : cmp[lane]; in V_NAME_F2()
143 ret[lane] = p; in V_NAME_F2()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUAtomicOptimizer.cpp10 /// This pass optimizes atomic operations by using a single lane of a wavefront
235 // If the pointer operand is divergent, then each lane is doing an atomic in visitAtomicRMWInst()
243 // If the value operand is divergent, each lane is contributing a different in visitAtomicRMWInst()
329 // If the value operand is divergent, each lane is contributing a different in visitIntrinsicInst()
439 // Pick an arbitrary lane from 0..31 and an arbitrary lane from 32..63 and in buildReduction()
481 // Combine lane 15 into lanes 16..31 (and, for wave 64, lane 47 into lanes in buildScan()
494 // Combine lane 31 into lanes 32..63. in buildScan()
534 // Copy the old lane 15 to the new lane 16. in buildShiftRight()
539 // Copy the old lane 31 to the new lane 32. in buildShiftRight()
544 // Copy the old lane 47 to the new lane 48. in buildShiftRight()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td256 // Register list of one D register, with byte lane subscripting.
266 // ...with half-word lane subscripting.
276 // ...with word lane subscripting.
287 // Register list of two D registers with byte lane subscripting.
297 // ...with half-word lane subscripting.
307 // ...with word lane subscripting.
317 // Register list of two Q registers with half-word lane subscripting.
327 // ...with word lane subscripting.
339 // Register list of three D registers with byte lane subscripting.
349 // ...with half-word lane subscripting.
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/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A Duncore-other.json1067 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
1080 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
1093 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
1106 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
1119 …ompletions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
1132 …ompletions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
1145 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
1158 …ompletions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
1182 …ion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
1194 …ion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane…
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/freebsd/sys/dev/hwpmc/
H A Dhwpmc_ppc970.c56 * Encoding 00 000 -- Add byte lane bit counters
59 * PMCxSEL: 1x -- select from byte lane: 10 == lower lane (0/1), 11 == upper
60 * lane (2/3).
61 * PMCxSEL[2:4] -- bit in the byte lane selected.
63 * PMC[1,2,5,6] == lane 0/lane 2
64 * PMC[3,4,7,8] == lane 1,3
68 * Lane 0 -- TTM0(FPU,ISU,IFU,VPU)
72 * Lane 1 -- TTM0
76 * Lane 2 -- TTM0
80 * Lane 3 -- TTM0
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dnvidia,tegra124-xusb-padctl.yaml15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
27 In addition to per-lane configuration, USB 3.0 ports may require additional
31 device tree node. Each lane exposed by the pad will be represented by its
32 own subnode and can be referenced by users of the lane using the standard
117 description: Function selection for this lane.
129 description: Function selection for this lane.
141 description: Function selection for this lane.
161 description: Function selection for this lane.
189 description: Function selection for this lane.
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H A Dphy-cadence-sierra.txt29 Each group of PHY lanes with a single master lane should be represented as
30 a sub-node. Note that the actual configuration of each lane is determined by
35 - reg: The master lane number. This is the lowest numbered lane
36 in the lane group.
38 master lane of the sub-node.

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