Lines Matching full:lane

15   signals) which connect directly to pins/pads on the SoC package. Each lane
18   and thus contains any logic common to all its lanes. Each lane can be
27   In addition to per-lane configuration, USB 3.0 ports may require additional
31   device tree node. Each lane exposed by the pad will be represented by its
32   own subnode and can be referenced by users of the lane using the standard
117                     description: Function selection for this lane.
129                     description: Function selection for this lane.
141                     description: Function selection for this lane.
161                     description: Function selection for this lane.
189                     description: Function selection for this lane.
201                     description: Function selection for this lane.
237                     description: Function selection for this lane.
249                     description: Function selection for this lane.
261                     description: Function selection for this lane.
273                     description: Function selection for this lane.
285                     description: Function selection for this lane.
313                     description: Function selection for this lane.