| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | intel,ixp4xx-expansion-peripheral-props.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
7 title: Peripheral properties for Intel IXP4xx Expansion Bus
10 The IXP4xx expansion bus controller handles access to devices on the
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
18 intel,ixp4xx-eb-t1:
23 intel,ixp4xx-eb-t2:
28 intel,ixp4xx-eb-t3:
33 intel,ixp4xx-eb-t4:
38 intel,ixp4xx-eb-t5:
43 intel,ixp4xx-eb-cycle-type:
[all …]
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| H A D | intel,ixp4xx-expansion-bus-controller.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
7 title: Intel IXP4xx Expansion Bus Controller
10 The IXP4xx expansion bus controller handles access to devices on the
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
37 description: The IXP4xx has a peculiar MMIO access scheme, as it changes
59 $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
87 compatible = "intel,ixp4xx-flash", "cfi-flash";
90 intel,ixp4xx-eb-t3 = <3>;
91 intel,ixp4xx-eb-cycle-type = <0>;
92 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
[all …]
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| /linux/arch/arm/boot/dts/intel/ixp/ |
| H A D | intel-ixp42x-arcom-vulcan.dts | 42 compatible = "intel,ixp4xx-flash", "cfi-flash";
55 intel,ixp4xx-eb-t3 = <3>;
56 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
57 intel,ixp4xx-eb-write-enable = <1>;
71 intel,ixp4xx-eb-t3 = <1>;
72 intel,ixp4xx-eb-t4 = <2>;
73 intel,ixp4xx-eb-ahb-split-transfers = <1>;
74 intel,ixp4xx-eb-write-enable = <1>;
75 intel,ixp4xx-eb-byte-access = <1>;
90 intel,ixp4xx-eb-t3 = <3>;
[all …]
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| H A D | intel-ixp42x-gateworks-gw2348.dts | 69 compatible = "intel,ixp4xx-flash", "cfi-flash";
72 intel,ixp4xx-eb-write-enable = <1>;
83 compatible = "intel,ixp4xx-compact-flash";
89 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
90 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
91 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
92 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
93 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
94 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
95 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
[all …]
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| H A D | intel-ixp42x-usrobotics-usr8200.dts | 88 compatible = "intel,ixp4xx-flash", "cfi-flash";
91 intel,ixp4xx-eb-write-enable = <1>;
109 intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
110 intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
111 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
112 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
113 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
114 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle
115 intel,ixp4xx-eb-byte-access-on-halfword = <0>;
116 intel,ixp4xx-eb-mux-address-and-data = <0>;
[all …]
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| H A D | intel-ixp4xx-reference-design.dtsi | 62 intel,ixp4xx-eb-t1 = <0>;
63 intel,ixp4xx-eb-t2 = <0>;
64 intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase
65 intel,ixp4xx-eb-t4 = <0>;
66 intel,ixp4xx-eb-t5 = <0>;
67 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
68 intel,ixp4xx-eb-byte-access-on-halfword = <0>;
69 intel,ixp4xx-eb-mux-address-and-data = <0>;
70 intel,ixp4xx-eb-ahb-split-transfers = <0>;
71 intel,ixp4xx-eb-write-enable = <1>;
[all …]
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| H A D | intel-ixp45x-ixp46x.dtsi | 6 * basic IXP4xx DTSI.
8 #include "intel-ixp4xx.dtsi"
29 * to present the IXP4xx as a device on a USB bus.
32 compatible = "intel,ixp4xx-udc";
39 compatible = "intel,ixp4xx-i2c";
47 compatible = "intel,ixp4xx-ethernet";
58 compatible = "intel,ixp4xx-ethernet";
69 compatible = "intel,ixp4xx-ethernet";
|
| H A D | intel-ixp43x-gateworks-gw2358.dts | 82 compatible = "intel,ixp4xx-flash", "cfi-flash";
85 intel,ixp4xx-eb-write-enable = <1>;
99 compatible = "intel,ixp4xx-compact-flash";
105 intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
106 intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
107 intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
108 intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
109 intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
110 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
111 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
[all …]
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| H A D | intel-ixp4xx.dtsi | 18 * The IXP4xx expansion bus is a set of up to 7 each up to 16MB
45 compatible = "intel,ixp4xx-ahb-queue-manager";
113 compatible = "intel,ixp4xx-gpio";
134 compatible = "intel,ixp4xx-timer";
140 compatible = "intel,ixp4xx-network-processing-engine";
147 compatible = "intel,ixp4xx-hss";
154 compatible = "intel,ixp4xx-hss";
162 compatible = "intel,ixp4xx-crypto";
171 compatible = "intel,ixp4xx-ethernet";
182 compatible = "intel,ixp4xx-ethernet";
[all …]
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| /linux/Documentation/devicetree/bindings/firmware/ |
| H A D | intel,ixp4xx-network-processing-engine.yaml | 5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
8 title: Intel IXP4xx Network Processing Engine
14 On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
17 on the IXP4xx platform. All IXP4xx platforms have three NPEs at
25 - const: intel,ixp4xx-network-processing-engine
34 $ref: /schemas/crypto/intel,ixp4xx-crypto.yaml#
48 $ref: /schemas/net/intel,ixp4xx-hss.yaml#
65 compatible = "intel,ixp4xx-network-processing-engine";
71 compatible = "intel,ixp4xx-hss";
88 compatible = "intel,ixp4xx-crypto";
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| /linux/Documentation/devicetree/bindings/gpio/ |
| H A D | intel,ixp4xx-gpio.yaml | 4 $id: http://devicetree.org/schemas/gpio/intel,ixp4xx-gpio.yaml#
7 title: Intel IXP4xx XScale Networking Processors GPIO Controller
10 This GPIO controller is found in the Intel IXP4xx
15 main IXP4xx interrupt controller which has a 1-to-1 mapping for
20 IXP4xx interrupt controller.
29 const: intel,ixp4xx-gpio
44 intel,ixp4xx-gpio14-clkout:
49 intel,ixp4xx-gpio15-clkout:
67 compatible = "intel,ixp4xx-gpio";
|
| /linux/Documentation/devicetree/bindings/ata/ |
| H A D | intel,ixp4xx-compact-flash.yaml | 4 $id: http://devicetree.org/schemas/ata/intel,ixp4xx-compact-flash.yaml#
7 title: Intel IXP4xx CompactFlash Card Controller
13 The IXP4xx network processors have a CompactFlash interface that presents
15 device is always connected to the expansion bus of the IXP4xx SoCs using one
17 node must be placed inside a chip select node on the IXP4xx expansion bus.
21 const: intel,ixp4xx-compact-flash
38 - $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
55 compatible = "intel,ixp4xx-compact-flash";
|
| /linux/Documentation/devicetree/bindings/net/ |
| H A D | intel,ixp4xx-ethernet.yaml | 5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#
8 title: Intel IXP4xx ethernet
17 The Intel IXP4xx ethernet makes use of the IXP4xx NPE (Network
18 Processing Engine) and the IXP4xx Queue Manager to process
24 const: intel,ixp4xx-ethernet
76 compatible = "intel,ixp4xx-network-processing-engine";
81 compatible = "intel,ixp4xx-ethernet";
91 compatible = "intel,ixp4xx-ethernet";
|
| H A D | intel,ixp4xx-hss.yaml | 5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#
8 title: Intel IXP4xx V.35 WAN High Speed Serial Link (HSS)
14 The Intel IXP4xx HSS makes use of the IXP4xx NPE (Network
15 Processing Engine) and the IXP4xx Queue Manager to process
20 const: intel,ixp4xx-hss
|
| /linux/Documentation/devicetree/bindings/misc/ |
| H A D | intel,ixp4xx-ahb-queue-manager.yaml | 5 $id: http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#
8 title: Intel IXP4xx AHB Queue Manager
14 The IXP4xx AHB Queue Manager maintains queues as circular buffers in
17 IXP4xx for accelerating queues, especially for networking. Clients pick
21 on a certain IXP4xx system will vary.
26 - const: intel,ixp4xx-ahb-queue-manager
48 compatible = "intel,ixp4xx-ahb-queue-manager";
|
| /linux/Documentation/arch/arm/ |
| H A D | ixp4xx.rst | 2 Release Notes for Linux on Intel's IXP4xx Network Processor
10 Intel's IXP4xx network processor is a highly integrated SOC that
13 consumption. The IXP4xx family currently consists of several processors
21 http://developer.intel.com/design/network/products/npfamily/ixp4xx.htm
23 Intel also made the IXCP1100 CPU for sometime which is an IXP4xx
28 Linux currently supports the following features on the IXP4xx chips:
35 See arch/arm/mach-ixp4xx/include/mach/platform.h for access functions.
56 - http://sourceforge.net/projects/ixp4xx-osdg/
69 The IXP4xx family allows for up to 256MB of memory but the PCI interface
76 IXP4xx provides two methods of accessing PCI memory space:
[all …]
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| /linux/drivers/soc/ixp4xx/ |
| H A D | Kconfig | 4 menu "IXP4xx SoC drivers"
7 tristate "IXP4xx Queue Manager support"
9 This driver supports IXP4xx built-in hardware queue manager
13 tristate "IXP4xx Network Processor Engine support"
17 This driver supports IXP4xx built-in network coprocessors
|
| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | intel,ixp4xx-timer.yaml | 5 $id: http://devicetree.org/schemas/timer/intel,ixp4xx-timer.yaml#
8 title: Intel IXP4xx XScale Networking Processors Timers
13 description: This timer is found in the Intel IXP4xx processors.
18 - const: intel,ixp4xx-timer
40 compatible = "intel,ixp4xx-timer";
|
| /linux/drivers/clocksource/ |
| H A D | timer-ixp4xx.c | 6 * Based on arch/arm/mach-ixp4xx/common.c
158 * IXP4xx timer tick
199 tmr->clkevt.name = "ixp4xx timer1"; in ixp4xx_timer_register()
210 IRQF_TIMER, "IXP4XX-TIMER1", tmr); in ixp4xx_timer_register()
231 .name = "ixp4xx-watchdog",
250 { .compatible = "intel,ixp4xx-timer", },
257 .name = "ixp4xx-timer",
272 pr_crit("IXP4xx: can't remap timer\n"); in ixp4xx_of_timer_init()
293 TIMER_OF_DECLARE(ixp4xx, "intel,ixp4xx-timer", ixp4xx_of_timer_init);
|
| /linux/drivers/bus/ |
| H A D | intel-ixp4xx-eb.c | 3 * Intel IXP4xx Expansion Bus Controller
93 .prop = "intel,ixp4xx-eb-t1",
99 .prop = "intel,ixp4xx-eb-t2",
105 .prop = "intel,ixp4xx-eb-t3",
111 .prop = "intel,ixp4xx-eb-t4",
117 .prop = "intel,ixp4xx-eb-t5",
123 .prop = "intel,ixp4xx-eb-byte-access-on-halfword",
128 .prop = "intel,ixp4xx-eb-hpi-hrdy-pol-high",
133 .prop = "intel,ixp4xx-eb-mux-address-and-data",
138 .prop = "intel,ixp4xx-eb-ahb-split-transfers",
[all …]
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| /linux/Documentation/devicetree/bindings/crypto/ |
| H A D | intel,ixp4xx-crypto.yaml | 5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
8 title: Intel IXP4xx cryptographic engine
14 The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
21 const: intel,ixp4xx-crypto
|
| /linux/drivers/char/hw_random/ |
| H A D | ixp4xx-rng.c | 3 * drivers/char/hw_random/ixp4xx-rng.c
5 * RNG driver for Intel IXP4xx family of NPUs
23 #include <linux/soc/ixp4xx/cpu.h>
37 .name = "ixp4xx",
67 .name = "ixp4xx-hwrandom",
|
| /linux/drivers/mtd/maps/ |
| H A D | physmap-ixp4xx.c | 3 * Intel IXP4xx OF physmap add-on
6 * Based on the ixp4xx.c map driver, originally written by:
17 #include "physmap-ixp4xx.h"
78 * The IXP4xx expansion bus only allows 16-bit wide acceses
121 if (!of_device_is_compatible(np, "intel,ixp4xx-flash")) in of_flash_probe_ixp4xx()
129 dev_info(dev, "initialized Intel IXP4xx-specific physmap control\n"); in of_flash_probe_ixp4xx()
|
| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | intel,ixp4xx-interrupt.yaml | 5 $id: http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#
8 title: Intel IXP4xx XScale Networking Processors Interrupt Controller
14 This interrupt controller is found in the Intel IXP4xx processors.
19 The distinct IXP4xx families with different interrupt controller
|
| /linux/drivers/irqchip/ |
| H A D | irq-ixp4xx.c | 3 * irqchip for the IXP4xx interrupt controller
6 * Based on arch/arm/mach-ixp4xx/common.c
169 * TODO: after converting IXP4xx to only device tree, set in ixp4xx_irq_domain_alloc()
198 * ixp4x_irq_setup() - Common setup code for the IXP4xx interrupt controller
232 ixi->irqchip.name = "IXP4xx"; in ixp4xx_irq_setup()
241 pr_crit("IXP4XX: can not add primary irqdomain\n"); in ixp4xx_irq_setup()
261 pr_crit("IXP4XX: could not ioremap interrupt controller\n"); in ixp4xx_of_init_irq()
273 pr_crit("IXP4XX: failed to set up irqchip\n"); in ixp4xx_of_init_irq()
|