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/linux/Documentation/devicetree/bindings/media/xilinx/
H A Dvideo.txt1 DT bindings for Xilinx video IP cores
2 -------------------------------------
4 Xilinx video IP cores process video streams by acting as video sinks and/or
8 Each video IP core is represented by an AMBA bus child node in the device
9 tree using bindings documented in this directory. Connections between the IP
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
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H A Dxlnx,video.txt1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
5 ---------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
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/linux/Documentation/networking/device_drivers/can/freescale/
H A Dflexcan.rst1 .. SPDX-License-Identifier: GPL-2.0+
7 Authors: Marc Kleine-Budde <mkl@pengutronix.de>,
13 For most flexcan IP cores the driver supports 2 RX modes:
15 - FIFO
16 - mailbox
18 The older flexcan cores (integrated into the i.MX25, i.MX28, i.MX35
20 configured for RX-FIFO mode.
28 cores come up in a mode where RTR reception is possible.
30 With the "rx-rtr" private flag the ability to receive RTR frames can
34 "rx-rtr" on
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/linux/Documentation/devicetree/bindings/
H A Dxilinx.txt1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10 Each IP-core has a set of parameters which the FPGA designer can use to
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
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/linux/drivers/media/platform/xilinx/
H A Dxilinx-vip.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Xilinx Video IP Core
5 * Copyright (C) 2013-2015 Ideas on Board
6 * Copyright (C) 2013-2015 Xilinx, Inc.
17 #include <media/v4l2-subdev.h>
22 * Minimum and maximum width and height common to most video IP cores. IP
23 * cores with different requirements must define their own values.
31 * Pad IDs. IP cores with multiple inputs or outputs should define their own
37 /* Xilinx Video IP Control Registers */
68 /* Xilinx Video IP Timing Registers */
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/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Di40e.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Overview
14 - Identifying Your Adapter
15 - Intel(R) Ethernet Flow Director
16 - Additional Configurations
17 - Known Issues
18 - Support
47 ----------------------
49 …intel.com/content/dam/www/public/us/en/documents/release-notes/xl710-ethernet-controller-feature-m…
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/linux/arch/arc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
90 source "arch/arc/plat-tb10x/Kconfig"
91 source "arch/arc/plat-axs10x/Kconfig"
92 source "arch/arc/plat-hsdk/Kconfig"
104 The original ARC ISA of ARC600/700 cores
110 ISA for the Next Generation ARC-HS cores
128 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
130 -Caches: New Prog Model, Region Flush
131 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
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/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,pruss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
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/linux/Documentation/networking/device_drivers/ethernet/stmicro/
H A Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
32 DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
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/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-grgpio.txt1 Aeroflex Gaisler GRGPIO General Purpose I/O cores.
3 The GRGPIO GPIO core is available in the GRLIB VHDL IP core library.
10 - name : Should be "GAISLER_GPIO" or "01_01a"
12 - reg : Address and length of the register set for the device
14 - interrupts : Interrupt numbers for this device
18 - nbits : The number of gpio lines. If not present driver assumes 32 lines.
20 - irqmap : An array with an index for each gpio line. An index is either a valid
25 For further information look in the documentation for the GLIB IP core library:
H A Dgpio-dsp-keystone.txt3 HOST OS userland running on ARM can send interrupts to DSP cores using
4 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
8 - 8 for C66x CorePacx CPUs 0-7
11 - each GPIO can be configured only as output pin;
12 - setting GPIO value to 1 causes IRQ generation on target DSP core;
13 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
17 - compatible: should be "ti,keystone-dsp-gpio"
18 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
21 - gpio-controller: Marks the device node as a gpio controller.
22 - #gpio-cells: Should be 2.
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dmtk,scp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tinghan Shen <tinghan.shen@mediatek.com>
13 This binding provides support for ARM Cortex M4 Co-processor found on some
19 - mediatek,mt8183-scp
20 - mediatek,mt8186-scp
21 - mediatek,mt8188-scp
22 - mediatek,mt8188-scp-dual
23 - mediatek,mt8192-scp
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H A Dti,pru-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI Programmable Realtime Unit (PRU) cores
10 - Suman Anna <s-anna@ti.com>
13 Each Programmable Real-Time Unit and Industrial Communication Subsystem
14 (PRU-ICSS or PRUSS) has two 32-bit load/store RISC CPU cores called
15 Programmable Real-Time Units (PRUs), each represented by a node. Each PRU
17 use the Data RAMs present within the PRU-ICSS for code execution.
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dti,keystone-irq.txt1 Keystone 2 IRQ controller IP
3 On Keystone SOCs, DSP cores can send interrupts to ARM
4 host using the IRQ controller IP. It provides 28 IRQ signals to ARM.
10 - compatible: should be "ti,keystone-irq"
11 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
14 - interrupt-controller : Identifies the node as an interrupt controller
15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
17 - interrupts: interrupt reference to primary interrupt controller
24 compatible = "ti,keystone-irq";
25 ti,syscon-dev = <&devctrl 0x2a0>;
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/linux/Documentation/devicetree/bindings/bus/
H A Dbaikal,bt1-axi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
23 accessible by means of the Baikal-T1 System Controller.
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/linux/drivers/gpu/drm/etnaviv/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
4 tristate "ETNAVIV (DRM support for Vivante GPU IP cores)"
/linux/drivers/net/ethernet/stmicro/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 If you have a network (Ethernet) card based on Synopsys Ethernet IP
12 Cores, say Y.
/linux/drivers/clocksource/
H A Darc_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
11 * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
18 #include <linux/clk-provider.h>
65 * MCIP_CMD/MCIP_READBACK however micro-architecturally there's in arc_read_gfrc()
68 * simultaneous read/write accesses from cores via those two registers. in arc_read_gfrc()
70 * trying to access two different sub-components (like GFRC, in arc_read_gfrc()
71 * inter-core interrupt, etc...). HW also supports simultaneously in arc_read_gfrc()
72 * accessing GFRC by multiple cores. in arc_read_gfrc()
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/linux/arch/arm/mach-exynos/
H A Dmcpm-exynos.c1 // SPDX-License-Identifier: GPL-2.0
5 // Based on arch/arm/mach-vexpress/dcscb.c
7 #include <linux/arm-cci.h>
12 #include <linux/soc/samsung/exynos-regs-pmu.h>
55 "r9", "r10", "ip", "lr", "memory")
65 return -EINVAL; in exynos_cpu_powerup()
71 * This assumes the cluster number of the big cores(Cortex A15) in exynos_cpu_powerup()
72 * is 0 and the Little cores(Cortex A7) is 1. in exynos_cpu_powerup()
81 * Before we reset the Little cores, we should wait in exynos_cpu_powerup()
87 timeout--; in exynos_cpu_powerup()
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/linux/Documentation/devicetree/bindings/usb/
H A Diproc-udc.txt5 on Synopsys Designware Cores AHB Subsystem Device Controller
6 IP.
9 - compatible: Add the compatibility strings for supported platforms.
10 For Broadcom NS2 platform, add "brcm,ns2-udc","brcm,iproc-udc".
11 For Broadcom Cygnus platform, add "brcm,cygnus-udc", "brcm,iproc-udc".
12 - reg: Offset and length of UDC register set
13 - interrupts: description of interrupt line
14 - phys: phandle to phy node.
18 compatible = "brcm,ns2-udc", "brcm,iproc-udc";
/linux/drivers/net/can/esd/
H A Desd_402_pci-core.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2015 - 2016 Thomas Körper, esd electronic system design gmbh
3 * Copyright (C) 2017 - 2023 Stefan Mätje, esd electronics gmbh
10 #include <linux/dma-mapping.h>
50 struct acc_core *cores; member
59 /* Used if the esdACC FPGA is built as CAN-Classic version. */
72 /* Used if the esdACC FPGA is built as CAN-FD version. */
103 irq_status = acc_card_interrupt(&card->ov, card->cores); in pci402_interrupt()
118 /* The FPGA hard IP PCIe core implements a 64-bit MSI Capability in pci402_set_msiconfig()
143 addr_lo |= 1; /* To enable 64-Bit addressing in PCIe endpoint */ in pci402_set_msiconfig()
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/linux/Documentation/devicetree/bindings/clock/
H A Dbaikal,bt1-ccu-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
23 2) PLLs clocks generators (PLLs) - described in this binding file.
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/linux/drivers/mcb/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 FPGA based devices. It is used to identify MCB based IP-Cores within
26 This is a MCB carrier on a PCI device. Both PCI attached on-board
30 If build as a module, the module is called mcb-pci.ko
39 If build as a module, the module is called mcb-lpc.ko
/linux/drivers/net/ethernet/synopsys/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
25 This driver supports the Synopsys DesignWare Cores Enterprise
26 Ethernet (dwc-xlgmac).
34 This selects the pci bus support for the dwc-xlgmac driver.
35 This driver was tested on Synopsys XLGMAC IP Prototyping Kit.
/linux/Documentation/devicetree/bindings/timer/
H A Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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