Lines Matching +full:ip +full:- +full:cores
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tinghan Shen <tinghan.shen@mediatek.com>
13 This binding provides support for ARM Cortex M4 Co-processor found on some
19 - mediatek,mt8183-scp
20 - mediatek,mt8186-scp
21 - mediatek,mt8188-scp
22 - mediatek,mt8188-scp-dual
23 - mediatek,mt8192-scp
24 - mediatek,mt8195-scp
25 - mediatek,mt8195-scp-dual
34 reg-names:
40 Clock for co-processor (see ../clock/clock-bindings.txt).
44 clock-names:
50 firmware-name:
57 memory-region:
60 cros-ec-rpmsg:
61 $ref: /schemas/mfd/google,cros-ec.yaml
68 - mediatek,rpmsg-name
72 '#address-cells':
75 '#size-cells':
84 "^scp@[a-f0-9]+$":
87 The MediaTek SCP integrated to SoC might be a multi-core version.
88 The other cores are represented as child nodes of the boot core.
89 There are some integration differences for the IP like the usage of
94 cores. The power of cache, SRAM and L1TCM power should be enabled
95 before booting SCP cores. The size of cache, SRAM, and L1TCM are varied
98 The SCP cores do not use an MMU, but has a set of registers to
99 control the translations between 32-bit CPU addresses into system bus
106 - mediatek,scp-core
112 reg-names:
118 firmware-name:
123 initializing sub cores of multi-core SCP.
125 memory-region:
128 cros-ec-rpmsg:
129 $ref: /schemas/mfd/google,cros-ec.yaml
136 - mediatek,rpmsg-name
141 - compatible
142 - reg
143 - reg-names
148 - compatible
149 - reg
150 - reg-names
153 - if:
157 - mediatek,mt8183-scp
158 - mediatek,mt8192-scp
161 - clocks
162 - clock-names
164 - if:
168 - mediatek,mt8183-scp
169 - mediatek,mt8186-scp
170 - mediatek,mt8188-scp
175 reg-names:
177 - const: sram
178 - const: cfg
179 - if:
183 - mediatek,mt8192-scp
184 - mediatek,mt8195-scp
189 reg-names:
191 - const: sram
192 - const: cfg
193 - const: l1tcm
194 - if:
198 - mediatek,mt8188-scp-dual
199 - mediatek,mt8195-scp-dual
204 reg-names:
206 - const: cfg
207 - const: l1tcm
212 - |
213 #include <dt-bindings/clock/mt8192-clk.h>
216 compatible = "mediatek,mt8192-scp";
220 reg-names = "sram", "cfg", "l1tcm";
222 clock-names = "main";
224 cros-ec-rpmsg {
225 compatible = "google,cros-ec-rpmsg";
226 mediatek,rpmsg-name = "cros-ec-rpmsg";
230 - |
232 compatible = "mediatek,mt8195-scp-dual";
235 reg-names = "cfg", "l1tcm";
237 #address-cells = <1>;
238 #size-cells = <1>;
242 compatible = "mediatek,scp-core";
244 reg-names = "sram";
246 cros-ec-rpmsg {
247 compatible = "google,cros-ec-rpmsg";
248 mediatek,rpmsg-name = "cros-ec-rpmsg";
253 compatible = "mediatek,scp-core";
255 reg-names = "sram";
257 cros-ec-rpmsg {
258 compatible = "google,cros-ec-rpmsg";
259 mediatek,rpmsg-name = "cros-ec-rpmsg";