/freebsd/sys/contrib/device-tree/Bindings/media/xilinx/ |
H A D | video.txt | 1 DT bindings for Xilinx video IP cores 2 ------------------------------------- 4 Xilinx video IP cores process video streams by acting as video sinks and/or 8 Each video IP core is represented by an AMBA bus child node in the device 9 tree using bindings documented in this directory. Connections between the IP 10 cores are represented as defined in ../video-interfaces.txt. 16 ----------------- 18 The following properties are common to all Xilinx video IP cores. 20 - xlnx,video-format: This property represents a video format transmitted on an 21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream [all …]
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H A D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP) 2 ------------------------------- 5 --------------- 7 Xilinx video IP pipeline processes video streams through one or more Xilinx 8 video IP cores. Each video IP core is represented as documented in video.txt 9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT 11 mappings between DMAs and the video IP cores. 15 - compatible: Must be "xlnx,video". 17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined 22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/ |
H A D | xilinx.txt | 1 d) Xilinx IP cores 3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use 10 Each IP-core has a set of parameters which the FPGA designer can use to 14 device drivers how the IP cores are configured, but it requires the kernel 20 properties of the device node. In general, device nodes for IP-cores 23 (name): (generic-name)@(base-address) { 24 compatible = "xlnx,(ip-core-name)-(HW_VER)" 27 interrupt-parent = <&interrupt-controller-phandle>; 29 xlnx,(parameter1) = "(string-value)"; 30 xlnx,(parameter2) = <(int-value)>; [all …]
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/freebsd/tools/tools/netrate/tcpp/ |
H A D | parallelism.csh | 4 # Run tcpp -s -p 8 on the server, then this on the client. 6 # Note awkwardly hard-coded IP address below. 12 set cores=8 16 set nips=4 # Number of local IP addresses to use 17 set baseip=192.168.100.200 # First IP address to use 19 foreach core (`jot $cores`) 23 echo -n $2,${core},${trial}, >> $1 24 ./tcpp -c 192.168.100.102 -p $core -b $totalbytes -m $mflag \ 25 -t $tflag -M $nips -l $baseip >> $1
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H A D | README | 1 tcpp -- Parallel TCP Exercise Tool 13 once, up to a maximum parallelism limit. The client can use one or many IP 14 addresses, in order to make more 4-tuples available for testing, and will 24 -s Select server mode 25 -p <numprocs> Number of workers, should be >= client -p arg 26 -r <baseport> Non-default base TCP port, should match client 27 -T Print CPU usage every ten seconds 28 -m <maxconnectionsperproc> Maximum simultaneous connections/proc, should 33 ./tcpp -s -p 4 -m 1000000 40 -c <remoteIP> Select client mode, and specific dest IP [all …]
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/freebsd/share/man/man4/ |
H A D | cxgbe.4 | 1 .\" Copyright (c) 2011-2016, Chelsio Inc 37 .Nd "Chelsio T4-, T5-, and T6-based 100Gb, 40Gb, 25Gb, 10Gb, and 1Gb Ethernet adapter driver" 42 .Bd -ragged -offset indent 49 .Bd -literal -offset indent 71 .Bl -column -offset indent "ASIC" "Port Name" "Parent Device" 82 adapter-wide MIBs under dev.t5nex. 84 dev.<port> for port MIBs and dev.<nexus> for adapter-wide MIBs. 93 .Bl -bullet -compact 95 Chelsio T6225-CR 97 Chelsio T6225-SO-CR [all …]
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H A D | bcma.4 | 35 .Bd -ragged -offset indent 42 .Bd -literal -offset indent 50 support for devices using the ARM AMBA-based backplane architecture found 56 These functional blocks, known as cores, use the ARM AMBA AXI or 59 The IP cores used in 73 .An -nosplit
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H A D | bhnd.4 | 34 .Bd -ragged -offset indent 40 .Bd -literal -offset indent 46 driver provides a unified kernel bus interface to the on-chip 51 and host-connected chipsets based on a common library of Broadcom IP 52 cores connected via an internal hardware bus architecture. 53 Drivers for these cores are implemented against the unified 62 The ARM AMBA-based interconnect used in later HND devices is supported by 77 .An -nosplit
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/freebsd/sys/contrib/device-tree/Bindings/soc/ti/ |
H A D | ti,pruss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 TI Programmable Real-Time Unit and Industrial Communication Subsystem 11 - Suman Anna <s-anna@ti.com> 15 The Programmable Real-Time Unit and Industrial Communication Subsystem 16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x, 17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC 18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and 23 peripheral interfaces, fast real-time responses, or specialized data handling. [all …]
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/freebsd/share/man/man9/ |
H A D | bhnd.9 | 1 .\" Copyright (c) 2015-2016 Landon Fuller <landonf@FreeBSD.org> 354 .Fa "const struct bhnd_core_info *cores" "u_int num_cores" 392 .Bd -literal 398 .Bd -literal 406 .Bd -literal 414 .Bd -literal 417 .Bd -literal 427 .Bd -literal 435 .Bd -literal 442 .Bd -literal [all …]
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/freebsd/sys/contrib/device-tree/Bindings/gpio/ |
H A D | gpio-grgpio.txt | 1 Aeroflex Gaisler GRGPIO General Purpose I/O cores. 3 The GRGPIO GPIO core is available in the GRLIB VHDL IP core library. 10 - name : Should be "GAISLER_GPIO" or "01_01a" 12 - reg : Address and length of the register set for the device 14 - interrupts : Interrupt numbers for this device 18 - nbits : The number of gpio lines. If not present driver assumes 32 lines. 20 - irqmap : An array with an index for each gpio line. An index is either a valid 25 For further information look in the documentation for the GLIB IP core library:
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H A D | gpio-dsp-keystone.txt | 3 HOST OS userland running on ARM can send interrupts to DSP cores using 4 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core. 8 - 8 for C66x CorePacx CPUs 0-7 11 - each GPIO can be configured only as output pin; 12 - setting GPIO value to 1 causes IRQ generation on target DSP core; 13 - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still 17 - compatible: should be "ti,keystone-dsp-gpio" 18 - ti,syscon-dev: phandle/offset pair. The phandle to syscon used to 21 - gpio-controller: Marks the device node as a gpio controller. 22 - #gpio-cells: Should be 2. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
H A D | ti,keystone-irq.txt | 1 Keystone 2 IRQ controller IP 3 On Keystone SOCs, DSP cores can send interrupts to ARM 4 host using the IRQ controller IP. It provides 28 IRQ signals to ARM. 10 - compatible: should be "ti,keystone-irq" 11 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to 14 - interrupt-controller : Identifies the node as an interrupt controller 15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt 17 - interrupts: interrupt reference to primary interrupt controller 24 compatible = "ti,keystone-irq"; 25 ti,syscon-dev = <&devctrl 0x2a0>; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/bus/ |
H A D | baikal,bt1-axi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Baikal-T1 AXI-bus 11 - Serge Semin <fancer.lancer@gmail.com> 14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all 15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600 16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so 23 accessible by means of the Baikal-T1 System Controller. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/remoteproc/ |
H A D | ti,pru-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/ti,pru-rpro [all...] |
H A D | ti,k3-r5f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5 [all...] |
/freebsd/sys/contrib/device-tree/Bindings/timer/ |
H A D | ti,c64x+timer64.txt | 2 ------- 8 - compatible: must be "ti,c64x+timer64" 9 - reg: base address and size of register region 10 - interrupts: interrupt id 14 - ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface. 16 - ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer. 21 ti,core-mask = < 0x01 >; 23 interrupt-parent = <&megamod_pic>;
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H A D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schema [all...] |
/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | baikal,bt1-ccu-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/clock/baikal,bt1-cc [all...] |
/freebsd/sys/contrib/device-tree/Bindings/usb/ |
H A D | iproc-udc.txt | 5 on Synopsys Designware Cores AHB Subsystem Device Controller 6 IP. 9 - compatible: Add the compatibility strings for supported platforms. 10 For Broadcom NS2 platform, add "brcm,ns2-udc","brcm,iproc-udc". 11 For Broadcom Cygnus platform, add "brcm,cygnus-udc", "brcm,iproc-udc". 12 - reg: Offset and length of UDC register set 13 - interrupts: description of interrupt line 14 - phys: phandle to phy node. 18 compatible = "brcm,ns2-udc", "brcm,iproc-udc";
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/freebsd/sys/contrib/device-tree/Bindings/pci/ |
H A D | designware-pcie.txt | 4 - compatible: 5 "snps,dw-pcie" for RC mode; 6 "snps,dw-pcie-ep" for EP mode; 7 - reg: For designware cores version < 4.80 contains the configuration 10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for 15 - #address-cells: set to <3> 16 - #size-cells: set to <2> 17 - device_type: set to "pci" 18 - ranges: ranges for the PCI memory and I/O regions 19 - #interrupt-cells: set to <1> [all …]
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/freebsd/sys/contrib/device-tree/Bindings/spi/ |
H A D | microchip,mpfs-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 fabric IP cores they are based on 14 - Conor Dooley <conor.dooley@microchip.com> 17 - $ref: spi-controller.yaml# 22 - items: 23 - const: microchip,mpfs-qspi 24 - const: microchip,coreqspi-rtl-v2 [all …]
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/freebsd/sys/contrib/device-tree/Bindings/media/ |
H A D | nxp,imx-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver 10 - Rui Miguel Silva <rmfrfs@gmail.com> 11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 13 description: |- 14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2 15 receiver IP core named CSIS. The IP core originates from Samsung, and may be [all …]
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H A D | nxp,imx7-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver 10 - Rui Miguel Silva <rmfrfs@gmail.com> 11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 13 description: |- 14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2 15 receiver IP core named CSIS. The IP core originates from Samsung, and may be [all …]
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/freebsd/secure/lib/libcrypto/man/man3/ |
H A D | OPENSSL_ia32cap.3 | 18 .\" Set up some character translations and predefined strings. \*(-- will 24 .tr \(*W- 27 . ds -- \(*W- 29 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch 30 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch 37 . ds -- \|\(em\| 50 .\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index 71 .\" Fear. Run. Save yourself. No user-serviceable parts. 81 . ds #H ((1u-(\\\\n(.fu%2u))*.13m) 97 . ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" [all …]
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