Lines Matching +full:ip +full:- +full:cores

1    d) Xilinx IP cores
3    The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10    Each IP-core has a set of parameters which the FPGA designer can use to
14    device drivers how the IP cores are configured, but it requires the kernel
20    properties of the device node.  In general, device nodes for IP-cores
23 	(name): (generic-name)@(base-address) {
24 		compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 		interrupt-parent = <&interrupt-controller-phandle>;
29 		xlnx,(parameter1) = "(string-value)";
30 		xlnx,(parameter2) = <(int-value)>;
33 	(generic-name):   an open firmware-style name that describes the
36 	(ip-core-name):	the name of the ip block (given after the BEGIN
38 			and all underscores '_' converted to dashes '-'.
43 			converted to dashes '-'.
46 	(size):		the address range size (often C_HIGHADDR - C_BASEADDR + 1).
48    Typically, the compatible list will include the exact IP core version
49    followed by an older IP core version which implements the same
78 		compatible = "xlnx,opb-uartlite-1.00.b";
80 		interrupt-parent = <&opb_intc_0>;
82 		current-speed = <d#115200>;	// standard serial device prop
83 		clock-frequency = <d#50000000>;	// standard serial device prop
84 		xlnx,data-bits = <8>;
85 		xlnx,odd-parity = <0>;
86 		xlnx,use-parity = <0>;
89    That covers the general approach to binding xilinx IP cores into the
98        - resolution = <xres yres> : pixel resolution of framebuffer.  Some
101        - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
103        - rotate-display (empty) : rotate display 180 degrees.
112        - 8-bit (empty) : Set this property for SystemACE in 8 bit mode
117       listed above, nodes for these devices should include a phy-handle
119       like local-mac-address.
126        - current-speed : Baud rate of uartlite
137 		- xlnx,family : The family of the FPGA, necessary since the
141 		- compatible : should contain "xlnx,xps-hwicap-1.00.a" or
142 				"xlnx,opb-hwicap-1.00.b".
150        - clock-frequency : Frequency of the clock input
151        - reg-offset : A value of 3 is required
152        - reg-shift : A value of 2 is required
157       base address for the EHCI registers, and it is always a big-endian
162       - xlnx,support-usb-fs: A value 0 means the core is built as high speed