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/linux/Documentation/devicetree/bindings/pci/
H A Dpci.txt3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
21 - max-link-speed:
24 unsupported link speed, for instance, trying to do training for
25 unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
27 - reset-gpios:
30 - supports-clkreq:
34 not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
[all …]
/linux/drivers/cpufreq/
H A De_powersaver.c1 // SPDX-License-Identifier: GPL-2.0-only
61 return -ENOMEM; in eps_acpi_init()
63 if (!zalloc_cpumask_var(&eps_acpi_cpu_perf->shared_cpu_map, in eps_acpi_init()
67 return -ENOMEM; in eps_acpi_init()
71 free_cpumask_var(eps_acpi_cpu_perf->shared_cpu_map); in eps_acpi_init()
74 return -EIO; in eps_acpi_init()
83 free_cpumask_var(eps_acpi_cpu_perf->shared_cpu_map); in eps_acpi_exit()
94 u32 lo, hi; in eps_get() local
103 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in eps_get()
104 return centaur->fsb * ((lo >> 8) & 0xff); in eps_get()
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H A Dlonghaul.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2001-2004 Dave Jones.
13 * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
16 * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
90 static char *print_speed(int speed) in print_speed() argument
92 if (speed < 1000) { in print_speed()
93 snprintf(speedbuffer, sizeof(speedbuffer), "%dMHz", speed); in print_speed()
97 if (speed%1000 == 0) in print_speed()
99 "%dGHz", speed/1000); in print_speed()
102 "%d.%dGHz", speed/1000, (speed%1000)/100); in print_speed()
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dusb251xb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip USB 2.0 Hi-Speed Hub Controller
10 - Richard Leitner <richard.leitner@skidata.com>
15 - microchip,usb2422
16 - microchip,usb2512b
17 - microchip,usb2512bi
18 - microchip,usb2513b
19 - microchip,usb2513bi
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H A Dmicrochip,usb5744.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip USB5744 4-port Hub Controller
10 Microchip's USB5744 SmartHubTM IC is a 4 port, SuperSpeed (SS)/Hi-Speed (HS),
12 Gen 1 specification. The USB5744 also supports Full Speed (FS) and Low Speed
19 - Michal Simek <michal.simek@amd.com>
20 - Mubin Sayyed <mubin.sayyed@amd.com>
21 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
26 - usb424,2744
[all …]
/linux/include/uapi/linux/usb/
H A Dch11.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
16 * From USB 2.0 spec Table 11-13, offset 7, a hub can
24 /* See USB 3.1 spec Table 10-5 */
36 * See USB 3.1 spec Table 10-12
44 * See USB 2.0 spec Table 11-16
53 * See USB 3.0 spec Table 10-6
60 * See USB 2.0 spec Table 11-17
67 * See USB 2.0 spec Table 11-17
88 * See USB 3.0 spec Table 10-7
102 /* USB 3.0 hub remote wake mask bits, see table 10-14 */
[all …]
/linux/arch/sparc/mm/
H A Dhypersparc.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * hypersparc.S: High speed Hypersparc mmu/cache operations.
10 #include <asm/asm-offsets.h>
29 sethi %hi(vac_cache_size), %g4
31 sethi %hi(vac_line_size), %g1
44 cmp %g1, -1
49 sethi %hi(vac_line_size), %g1
51 sethi %hi(vac_cache_size), %g2
82 cmp %g1, -1
87 sethi %hi(vac_line_size), %g1
[all …]
H A Dviking.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * viking.S: High speed Viking cache/mmu operations
12 #include <asm/asm-offsets.h>
39 sethi %hi(PAGE_OFFSET), %g2
43 clr %o1 ! set counter, 0 - 127
44 sethi %hi(PAGE_OFFSET + PAGE_SIZE - 0x80000000), %o3
45 sethi %hi(0x80000000), %o4
46 sethi %hi(VIKING_PTAG_VALID), %o5
47 sethi %hi(2*PAGE_SIZE), %o0
48 sethi %hi(PAGE_SIZE), %g7
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H A Dtsunami.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * tsunami.S: High speed MicroSparc-I mmu/cache operations.
9 #include <asm/asm-offsets.h>
31 cmp %g2, -1
53 cmp %g2, -1
72 andn %o1, (PAGE_SIZE - 1), %o1
73 cmp %o3, -1
98 /* NOTE: This routine has to be shorter than 70insns --jj */
116 sethi %hi(__copy_1page), %o0
118 sethi %hi(tsunami_copy_1page), %o1
[all …]
/linux/arch/mips/loongson2ef/lemote-2f/
H A Dreset.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Board-specific reboot/shutdown routines
24 * reset cpu to full speed, this is needed when enabling cpu frequency in reset_cpu()
44 u32 hi, lo; in fl2f_reboot() local
45 _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo); in fl2f_reboot()
47 _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo); in fl2f_reboot()
53 u32 hi, lo, val; in fl2f_shutdown() local
57 _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo); in fl2f_shutdown()
113 /* cpu-gpio0 output low */ in yl2f89_shutdown()
115 /* cpu-gpio0 as output */ in yl2f89_shutdown()
/linux/drivers/char/hw_random/
H A Dvia-rng.c71 * instead of the current u8-at-a-time.
89 char buf[16 + PADLOCK_ALIGNMENT - STACK_ALIGN] __attribute__ in via_rng_data_present()
95 /* We choose the recommended 1-byte-per-instruction RNG rate, in via_rng_data_present()
96 * for greater randomness at the expense of speed. Larger in via_rng_data_present()
97 * values 2, 4, or 8 bytes-per-instruction yield greater in via_rng_data_present()
98 * speed at lesser randomness. in via_rng_data_present()
101 * change the ->n_bytes values in rng_vendor_ops[] tables. in via_rng_data_present()
116 rng->priv = *via_rng_datum; in via_rng_data_present()
122 u32 via_rng_datum = (u32)rng->priv; in via_rng_data_read()
132 u32 lo, hi, old_lo; in via_rng_init() local
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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,usb-hs-28nm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13 Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
18 - qcom,usb-hs-28nm-femtophy
23 "#phy-cells":
28 - description: rpmcc ref clock
[all …]
/linux/drivers/net/ethernet/ti/icssg/
H A Dicssg_switch_map.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
49 /* VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000 */
52 /* VLAN-FID Table offset for EMAC */
88 /* IEP count hi roll over count */
91 /* IEP count hi sw counter */
112 /* pktTxDelay for P1 = link speed dependent p1 mac delay + p1 phy delay */
115 /* pktTxDelay for P2 = link speed dependent p2 mac delay + p2 phy delay */
173 * cut-through/S&F.
180 /* Used to notify the FW of the current link speed */
[all …]
/linux/drivers/net/ethernet/xscale/
H A Dixp4xx_eth.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
13 * RX-free queue 26 27 28
14 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
17 * bits 0 -> 1 - NPE ID (RX and TX-done)
18 * bits 0 -> 2 - priority (TX, per 802.1D)
19 * bits 3 -> 4 - port ID (user-set?)
20 * bits 5 -> 31 - physical descriptor address
24 #include <linux/dma-mapping.h>
75 #define MAX_MRU (14320 - VLAN_ETH_HLEN)
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_hw.c1 // SPDX-License-Identifier: GPL-2.0
25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
41 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
43 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
45 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
46 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
[all …]
/linux/drivers/usb/dwc2/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
10 Say Y here if your system has a Dual Role Hi-Speed USB
18 dwc2_platform.ko. For all modes(host, gadget and dual-role), there
33 The Designware USB2.0 high-speed host controller
35 driver to operate in Host-only mode.
37 comment "Gadget/Dual-role mode requires USB Gadget support to be enabled"
43 The Designware USB2.0 high-speed gadget controller
45 driver to operate in Peripheral-only mode. This option requires
52 Select this option if you want the driver to work in a dual-role
54 the role will be determined by the cable that gets plugged-in. This
[all …]
/linux/drivers/net/ethernet/atheros/atlx/
H A Datl1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
8 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
21 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
37 #include <linux/dma-mapping.h>
84 #define OPTION_UNSET -1
93 * Valid Range: 10-65535
131 *value = opt->def; in atl1_validate_option()
[all …]
/linux/drivers/phy/qualcomm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
124 controllers on Qualcomm chips. This driver supports the high-speed
133 Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm
142 Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm
160 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
163 Support for the USB high-speed ULPI compliant phy on Qualcomm
171 Enable support for the USB high-speed SNPS Femto phy on Qualcomm
184 tristate "Qualcomm 28nm High-Speed PHY"
186 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dvsc7326_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Straight off the data sheet, VMDS-10038 Rev 2.0 and
9 * PD0011-01-14-Meigs-II 2002-12-12
26 #define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */
58 #define BIST_ERR_CNT_MSB 0x04 /* BIST error count hi 8b */
60 #define BIST_ERR_SEL_MSB 0x06 /* BIST error select hi 8b */
65 #define BIST_ERR_ADR3 0x0b /* BIST error address hi 8b */
69 * fn = FIFO number, 0-9
84 * bn = bucket number 0-10 (yes, 11 buckets)
96 #define REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e) /* FIFO SRAM data hi 8b */
[all …]
H A Dpm3393.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
14 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
87 t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
93 t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
115 /* PM3393 - Enabling all hardware block interrupts. in pm3393_interrupt_enable()
138 /* PM3393 - Global interrupt enable in pm3393_interrupt_enable()
144 /* TERMINATOR - PL_INTERUPTS_EXT */ in pm3393_interrupt_enable()
145 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
147 writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
[all …]
/linux/Documentation/usb/
H A Diuu_phoenix.rst5 Hi all,
10 bring a ttyUSB[0-x] interface. This driver must be
23 How to tune the reader speed?
50 - clockmode will provide 3 different base settings commonly adopted by
57 - boost provide a way to overclock the reader ( my favorite :-) )
64 the speed to a score 10 to 20% better than the simple clockmode=3 !!!
67 - cdmode permit to setup the signal used to inform the userland ( ioctl answer )
70 - xmas is completely useless except for your eyes. This is one of my friend who was
75 - debug will produce a lot of debugging messages...
82 is an abstraction, so use any speed or parity setting will
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmicrochip,ksz.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
11 - Woojung Huh <Woojung.Huh@microchip.com>
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
21 - microchip,ksz8765
22 - microchip,ksz8794
23 - microchip,ksz8795
24 - microchip,ksz8863
[all …]
/linux/arch/sparc/kernel/
H A Detrap_32.S1 /* SPDX-License-Identifier: GPL-2.0 */
54 * to call c-code and the trap cannot be handled in-window)
57 * sethi %hi(trap_setup), %l4
63 * -----
131 #define STACK_OFFSET (THREAD_SIZE - TRACEREG_SZ - STACKFRAME_SZ)
137 sethi %hi(STACK_OFFSET), %t_twinmask
149 we can speed this up. */
150 sethi %hi(STACK_OFFSET), %curptr
154 sethi %hi(~(THREAD_SIZE - 1)), %curptr
158 /* Clear current_thread_info->w_saved */
[all …]
/linux/drivers/usb/serial/
H A Dftdi_sio_ids.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Philipp Gühring - pg@futureware.at - added the Device ID of the USB relais
25 #define FTDI_4232H_PID 0x6011 /* Quad channel hi-speed device */
26 #define FTDI_232H_PID 0x6014 /* Single channel hi-speed device */
27 #define FTDI_FTX_PID 0x6015 /* FT-X series (FT201X, FT230X, FT231X, etc) */
28 #define FTDI_FT2233HP_PID 0x6040 /* Dual channel hi-speed device with PD */
29 #define FTDI_FT4233HP_PID 0x6041 /* Quad channel hi-speed device with PD */
30 #define FTDI_FT2232HP_PID 0x6042 /* Dual channel hi-speed device with PD */
31 #define FTDI_FT4232HP_PID 0x6043 /* Quad channel hi-speed device with PD */
32 #define FTDI_FT233HP_PID 0x6044 /* Dual channel hi-speed device with PD */
[all …]
/linux/drivers/usb/gadget/udc/
H A Dm66592-udc.h1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2006-2007 Renesas Solutions Corp.
17 #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */
26 #define M66592_HSE 0x0080 /* b7: Hi-speed enable */
28 #define M66592_DMRPD 0x0020 /* b5: D- pull down control */
30 #define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */
35 #define M66592_LNST 0x0003 /* b1-0: D+, D- line status */
47 #define M66592_RHST 0x0003 /* b1-0: Reset handshake status */
48 #define M66592_HSMODE 0x0003 /* Hi-Speed mode */
49 #define M66592_FSMODE 0x0002 /* Full-Speed mode */
[all …]

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