/linux/Documentation/devicetree/bindings/mfd/ |
H A D | omap-usb-host.txt | 5 - compatible: should be "ti,usbhs-host" 6 - reg: should contain one register range i.e. start and length 7 - ti,hwmods: must contain "usb_host_hs" 11 - num-ports: number of USB ports. Usually this is automatically detected 15 - portN-mode: String specifying the port mode for port N, where N can be 16 from 1 to 3. If the port mode is not specified, that port is treated 18 "ehci-phy", 19 "ehci-tll", 20 "ehci-hsic", 21 "ohci-phy-6pin-datse0", [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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/linux/drivers/phy/tegra/ |
H A D | xusb.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved. 31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate() 32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate() 34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate() 35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate() 38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate() 39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate() 45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate() 53 .compatible = "nvidia,tegra124-xusb-padctl", [all …]
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H A D | xusb-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. 27 ((x) ? (11 + ((x) - 1) * 6) : 0) 451 for (map = tegra210_usb3_map; map->type; map++) { in tegra210_usb3_lane_map() 452 if (map->index == lane->index && in tegra210_usb3_lane_map() 453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map() 454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map() 455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map() 456 return map->port; in tegra210_usb3_lane_map() 460 return -EINVAL; in tegra210_usb3_lane_map() [all …]
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/linux/drivers/phy/samsung/ |
H A D | phy-exynos5250-usb2.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support 13 #include "phy-samsung-usb2.h" 124 /* Mode switch register */ 168 return -EINVAL; in exynos5250_rate_to_clk() 176 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos5250_isol() 180 if (drv->cfg == &exynos5250_usb2_phy_config && in exynos5250_isol() 181 inst->cfg->id == EXYNOS5250_DEVICE) in exynos5250_isol() 183 else if (drv->cfg == &exynos5250_usb2_phy_config && in exynos5250_isol() 184 inst->cfg->id == EXYNOS5250_HOST) in exynos5250_isol() [all …]
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/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-usb-hsic.c | 1 // SPDX-License-Identifier: GPL-2.0-only 10 #include <linux/pinctrl/pinctrl-state.h> 29 struct ulpi *ulpi = uphy->ulpi; in qcom_usb_hsic_phy_power_on() 33 ret = clk_prepare_enable(uphy->phy_clk); in qcom_usb_hsic_phy_power_on() 37 ret = clk_prepare_enable(uphy->cal_clk); in qcom_usb_hsic_phy_power_on() 41 ret = clk_prepare_enable(uphy->cal_sleep_clk); in qcom_usb_hsic_phy_power_on() 55 /* Configure pins for HSIC functionality */ in qcom_usb_hsic_phy_power_on() 56 pins_default = pinctrl_lookup_state(uphy->pctl, PINCTRL_STATE_DEFAULT); in qcom_usb_hsic_phy_power_on() 62 ret = pinctrl_select_state(uphy->pctl, pins_default); in qcom_usb_hsic_phy_power_on() 66 /* Enable HSIC mode in HSIC_CFG register */ in qcom_usb_hsic_phy_power_on() [all …]
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H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s. 111 PHY transceivers working only in USB3 mode on Qualcomm chips. This 124 controllers on Qualcomm chips. This driver supports the high-speed 133 Enable support for the USB high-speed eUSB2 repeater on Qualcomm 146 host only mode configurations. 174 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in 177 Support for the USB high-speed ULPI compliant phy on Qualcomm 185 Enable support for the USB high-speed SNPS Femto phy on Qualcomm 191 tristate "Qualcomm USB HSIC ULPI PHY module" [all …]
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/linux/drivers/usb/chipidea/ |
H A D | ci_hdrc_imx.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 15 /* true if over-current polarity is active low */ 24 unsigned int hsic:1; /* HSIC controller */ member 28 enum usb_dr_mode available_role; /* runtime usb dr mode */
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H A D | usbmisc_imx.c | 1 // SPDX-License-Identifier: GPL-2.0+ 82 /* HSIC enable */ 84 /* Force HSIC module 480M clock on, even when in Host is in suspend mode */ 88 /* For imx6dql, it is host-only controller, for later imx6, it is otg's */ 106 /* The default DM/DP value is pull-down */ 203 struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev); in usbmisc_imx25_init() 207 if (data->index > 1) in usbmisc_imx25_init() 208 return -EINVAL; in usbmisc_imx25_init() 210 spin_lock_irqsave(&usbmisc->lock, flags); in usbmisc_imx25_init() 211 switch (data->index) { in usbmisc_imx25_init() [all …]
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H A D | ci_hdrc_imx.c | 1 // SPDX-License-Identifier: GPL-2.0+ 87 { .compatible = "fsl,imx23-usb", .data = &imx23_usb_data}, 88 { .compatible = "fsl,imx28-usb", .data = &imx28_usb_data}, 89 { .compatible = "fsl,imx27-usb", .data = &imx27_usb_data}, 90 { .compatible = "fsl,imx6q-usb", .data = &imx6q_usb_data}, 91 { .compatible = "fsl,imx6sl-usb", .data = &imx6sl_usb_data}, 92 { .compatible = "fsl,imx6sx-usb", .data = &imx6sx_usb_data}, 93 { .compatible = "fsl,imx6ul-usb", .data = &imx6ul_usb_data}, 94 { .compatible = "fsl,imx7d-usb", .data = &imx7d_usb_data}, 95 { .compatible = "fsl,imx7ulp-usb", .data = &imx7ulp_usb_data}, [all …]
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/linux/Documentation/devicetree/bindings/soc/tegra/ |
H A D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jonathan Hunter <jonathanh@nvidia.com> 16 - nvidia,tegra20-pmc 17 - nvidia,tegra30-pmc 18 - nvidia,tegra114-pmc 19 - nvidia,tegra124-pmc [all …]
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/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | qcom,msm8974-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8974-pinctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Bjorn Andersson <andersson@kernel.org> 11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 14 Top Level Mode Multiplexer pin controller in Qualcomm MSM8974 SoC. 18 const: qcom,msm8974-pinctrl 26 gpio-reserved-ranges: 30 gpio-line-names: [all …]
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H A D | nvidia,tegra124-xusb-padctl.txt | 7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt. 14 This document defines the device-specific binding for the XUSB pad controller. 16 Refer to pinctrl-bindings.txt in this directory for generic information about 17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on 21 -------------------- 22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl". 23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl", 24 "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210. 25 - reg: Physical base address and length of the controller's registers. 26 - resets: Must contain an entry for each entry in reset-names. [all …]
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/linux/drivers/gpu/drm/bridge/ |
H A D | sil-sii8620.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 9 * Copyright (C) 2013-2014 Silicon Image, Inc. 82 /* Video Mode, default value: 0x00 */ 86 /* Video Input Mode, default value: 0xc0 */ 323 /* I2C Device Address re-assignment */ 338 /* HSIC RX Control3, default value: 0x07 */ 345 /* HSIC RX INT Registers */ 417 /* HSIC TX CRTL, default value: 0x00 */ 425 /* HSIC TX INT Low, default value: 0x00 */ 428 /* HSIC TX INT High, default value: 0x00 */ [all …]
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/linux/drivers/usb/phy/ |
H A D | of.c | 1 // SPDX-License-Identifier: GPL-2.0+ 18 [USBPHY_INTERFACE_MODE_HSIC] = "hsic", 22 * of_usb_get_phy_mode - Get phy mode for given device_node
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/linux/drivers/usb/misc/ |
H A D | usb4604.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Driver for SMSC USB4604 USB HSIC 4-port 2.0 hub controller driver 6 * Copyright (c) 2012-2013 Dongjin Kim (tobetter@gmail.com) 23 enum usb4604_mode mode; member 30 gpiod_set_value_cansleep(hub->gpio_reset, state); in usb4604_reset() 39 struct device *dev = hub->dev; in usb4604_connect() 52 hub->mode = USB4604_MODE_HUB; in usb4604_connect() 53 dev_dbg(dev, "switched to HUB mode\n"); in usb4604_connect() 58 static int usb4604_switch_mode(struct usb4604 *hub, enum usb4604_mode mode) in usb4604_switch_mode() argument 60 struct device *dev = hub->dev; in usb4604_switch_mode() [all …]
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/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos4412-itop-scp-core.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 13 #include <dt-bindings/clock/samsung,s2mps11.h> 14 #include <dt-bindings/gpio/gpio.h> 15 #include <dt-bindings/input/input.h> 17 #include "exynos4412-ppmu-common.dtsi" 18 #include "exynos-mfc-reserved-memory.dtsi" 31 compatible = "samsung,secure-firmware"; 35 fixed-rate-clocks { 37 compatible = "samsung,clock-xxti"; 38 clock-frequency = <0>; [all …]
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/linux/drivers/phy/allwinner/ |
H A D | phy-sun4i-usb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 5 * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com> 18 #include <linux/extcon-provider.h> 27 #include <linux/phy/phy-sun4i-usb.h> 84 /* A83T specific control bits for PHY2 HSIC */ 145 container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index]) 153 iscr = readl(data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr() 156 writel(iscr, data->base + REG_ISCR); in sun4i_usb_phy0_update_iscr() 183 u32 temp, usbc_bit = BIT(phy->index * 2); in sun4i_usb_phy_write() 184 void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset; in sun4i_usb_phy_write() [all …]
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/linux/arch/arm/boot/dts/allwinner/ |
H A D | sun9i-a80-optimus.dts | 2 * Copyright 2014 Chen-Yu Tsai 4 * Chen-Yu Tsai <wens@csie.org> 6 * This file is dual-licensed: you can use it either under the terms 45 /dts-v1/; 46 #include "sun9i-a80.dtsi" 48 #include <dt-bindings/gpio/gpio.h> 52 compatible = "merrii,a80-optimus", "allwinner,sun9i-a80"; 60 stdout-path = "serial0:115200n8"; 64 compatible = "gpio-leds"; 83 reg_usb1_vbus: usb1-vbus { [all …]
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/linux/arch/arm/boot/dts/ti/omap/ |
H A D | omap5-board-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 6 #include <dt-bindings/interrupt-controller/irq.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 15 stdout-path = &uart3; 18 vmain: fixedregulator-vmain { 19 compatible = "regulator-fixed"; 20 regulator-name = "vmain"; 21 regulator-min-microvolt = <5000000>; 22 regulator-max-microvolt = <5000000>; [all …]
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/linux/arch/arm/boot/dts/marvell/ |
H A D | mmp3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 6 #include <dt-bindings/clock/marvell,mmp2.h> 7 #include <dt-bindings/power/marvell,mmp2.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #address-cells = <1>; 12 #size-cells = <1>; 15 #address-cells = <1>; 16 #size-cells = <0>; 17 enable-method = "marvell,mmp3-smp"; 22 next-level-cache = <&l2>; [all …]
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/linux/drivers/mfd/ |
H A D | omap-usb-host.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI 5 * Copyright (C) 2011-2013 Texas Instruments Incorporated - https://www.ti.com 15 #include <linux/dma-mapping.h> 17 #include <linux/platform_data/usb-omap.h> 23 #include "omap-usb.h" 26 #define OMAP_EHCI_DEVICE "ehci-omap" 27 #define OMAP_OHCI_DEVICE "ohci-omap3" 56 /* OMAP4-specific defines */ 72 /* Values of UHH_REVISION - Note: these are not given in the TRM */ [all …]
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/linux/Documentation/devicetree/bindings/usb/ |
H A D | atmel-usb.txt | 6 - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers 7 used in host mode. 8 - reg: Address and length of the register set for the device 9 - interrupts: Should contain ohci interrupt 10 - clocks: Should reference the peripheral, host and system clocks 11 - clock-names: Should contain three strings 15 - num-ports: Number of ports. 16 - atmel,vbus-gpio: If present, specifies a gpio that needs to be 18 - atmel,oc-gpio: If present, specifies a gpio that needs to be 22 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; [all …]
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