xref: /linux/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt (revision 664b0bae0b87f69bc9deb098f5e0158b9cf18e04)
1be306dacSThierry RedingDevice tree binding for NVIDIA Tegra XUSB pad controller
2be306dacSThierry Reding========================================================
3be306dacSThierry Reding
4b1accd10SThierry RedingNOTE: It turns out that this binding isn't an accurate description of the XUSB
5b1accd10SThierry Redingpad controller. While the description is good enough for the functional subset
6b1accd10SThierry Redingrequired for PCIe and SATA, it lacks the flexibility to represent the features
7b1accd10SThierry Redingneeded for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
8b1accd10SThierry RedingThe binding described in this file is deprecated and should not be used.
9b1accd10SThierry Reding
10be306dacSThierry RedingThe Tegra XUSB pad controller manages a set of lanes, each of which can be
11be306dacSThierry Redingassigned to one out of a set of different pads. Some of these pads have an
12be306dacSThierry Redingassociated PHY that must be powered up before the pad can be used.
13be306dacSThierry Reding
14be306dacSThierry RedingThis document defines the device-specific binding for the XUSB pad controller.
15be306dacSThierry Reding
16be306dacSThierry RedingRefer to pinctrl-bindings.txt in this directory for generic information about
17be306dacSThierry Redingpin controller device tree bindings and ../phy/phy-bindings.txt for details on
18be306dacSThierry Redinghow to describe and reference PHYs in device trees.
19be306dacSThierry Reding
20be306dacSThierry RedingRequired properties:
21be306dacSThierry Reding--------------------
22193c9d23SPaul Walmsley- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23193c9d23SPaul Walmsley  Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
24193c9d23SPaul Walmsley  "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
25be306dacSThierry Reding- reg: Physical base address and length of the controller's registers.
26be306dacSThierry Reding- resets: Must contain an entry for each entry in reset-names.
27be306dacSThierry Reding  See ../reset/reset.txt for details.
28be306dacSThierry Reding- reset-names: Must include the following entries:
29be306dacSThierry Reding  - padctl
30be306dacSThierry Reding- #phy-cells: Should be 1. The specifier is the index of the PHY to reference.
31be306dacSThierry Reding  See <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> for the list of valid values.
32be306dacSThierry Reding
33be306dacSThierry RedingLane muxing:
34be306dacSThierry Reding------------
35be306dacSThierry Reding
36be306dacSThierry RedingChild nodes contain the pinmux configurations following the conventions from
37be306dacSThierry Redingthe pinctrl-bindings.txt document. Typically a single, static configuration is
38be306dacSThierry Redinggiven and applied at boot time.
39be306dacSThierry Reding
40be306dacSThierry RedingEach subnode describes groups of lanes along with parameters and pads that
41be306dacSThierry Redingthey should be assigned to. The name of these subnodes is not important. All
42be306dacSThierry Redingsubnodes should be parsed solely based on their content.
43be306dacSThierry Reding
44be306dacSThierry RedingEach subnode only applies the parameters that are explicitly listed. In other
45be306dacSThierry Redingwords, if a subnode that lists a function but no pin configuration parameters
46be306dacSThierry Redingimplies no information about any pin configuration parameters. Similarly, a
47be306dacSThierry Redingsubnode that describes only an IDDQ parameter implies no information about
48be306dacSThierry Redingwhat function the pins are assigned to. For this reason even seemingly boolean
49be306dacSThierry Redingvalues are actually tristates in this binding: unspecified, off or on.
50be306dacSThierry RedingUnspecified is represented as an absent property, and off/on are represented
51be306dacSThierry Redingas integer values 0 and 1.
52be306dacSThierry Reding
53be306dacSThierry RedingRequired properties:
54be306dacSThierry Reding- nvidia,lanes: An array of strings. Each string is the name of a lane.
55be306dacSThierry Reding
56be306dacSThierry RedingOptional properties:
57be306dacSThierry Reding- nvidia,function: A string that is the name of the function (pad) that the
58be306dacSThierry Reding  pin or group should be assigned to. Valid values for function names are
59be306dacSThierry Reding  listed below.
60be306dacSThierry Reding- nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes)
61be306dacSThierry Reding
62be306dacSThierry RedingNote that not all of these properties are valid for all lanes. Lanes can be
63be306dacSThierry Redingdivided into three groups:
64be306dacSThierry Reding
65be306dacSThierry Reding  - otg-0, otg-1, otg-2:
66be306dacSThierry Reding
67be306dacSThierry Reding    Valid functions for this group are: "snps", "xusb", "uart", "rsvd".
68be306dacSThierry Reding
69be306dacSThierry Reding    The nvidia,iddq property does not apply to this group.
70be306dacSThierry Reding
71be306dacSThierry Reding  - ulpi-0, hsic-0, hsic-1:
72be306dacSThierry Reding
73be306dacSThierry Reding    Valid functions for this group are: "snps", "xusb".
74be306dacSThierry Reding
75be306dacSThierry Reding    The nvidia,iddq property does not apply to this group.
76be306dacSThierry Reding
77be306dacSThierry Reding  - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0:
78be306dacSThierry Reding
79be306dacSThierry Reding    Valid functions for this group are: "pcie", "usb3", "sata", "rsvd".
80be306dacSThierry Reding
81be306dacSThierry Reding
82be306dacSThierry RedingExample:
83be306dacSThierry Reding========
84be306dacSThierry Reding
85be306dacSThierry RedingSoC file extract:
86be306dacSThierry Reding-----------------
87be306dacSThierry Reding
88f43521e9SThierry Reding	padctl@7009f000 {
89be306dacSThierry Reding		compatible = "nvidia,tegra124-xusb-padctl";
90be306dacSThierry Reding		reg = <0x0 0x7009f000 0x0 0x1000>;
91be306dacSThierry Reding		resets = <&tegra_car 142>;
92be306dacSThierry Reding		reset-names = "padctl";
93be306dacSThierry Reding
94be306dacSThierry Reding		#phy-cells = <1>;
95be306dacSThierry Reding	};
96be306dacSThierry Reding
97be306dacSThierry RedingBoard file extract:
98be306dacSThierry Reding-------------------
99be306dacSThierry Reding
100*48c926cdSMarco Franchi	pcie-controller@1003000 {
101be306dacSThierry Reding		...
102be306dacSThierry Reding
103be306dacSThierry Reding		phys = <&padctl 0>;
104be306dacSThierry Reding		phy-names = "pcie";
105be306dacSThierry Reding
106be306dacSThierry Reding		...
107be306dacSThierry Reding	};
108be306dacSThierry Reding
109be306dacSThierry Reding	...
110be306dacSThierry Reding
111f43521e9SThierry Reding	padctl: padctl@7009f000 {
112be306dacSThierry Reding		pinctrl-0 = <&padctl_default>;
113be306dacSThierry Reding		pinctrl-names = "default";
114be306dacSThierry Reding
115be306dacSThierry Reding		padctl_default: pinmux {
116be306dacSThierry Reding			usb3 {
117be306dacSThierry Reding				nvidia,lanes = "pcie-0", "pcie-1";
118be306dacSThierry Reding				nvidia,function = "usb3";
119be306dacSThierry Reding				nvidia,iddq = <0>;
120be306dacSThierry Reding			};
121be306dacSThierry Reding
122be306dacSThierry Reding			pcie {
123be306dacSThierry Reding				nvidia,lanes = "pcie-2", "pcie-3",
124be306dacSThierry Reding					       "pcie-4";
125be306dacSThierry Reding				nvidia,function = "pcie";
126be306dacSThierry Reding				nvidia,iddq = <0>;
127be306dacSThierry Reding			};
128be306dacSThierry Reding
129be306dacSThierry Reding			sata {
130be306dacSThierry Reding				nvidia,lanes = "sata-0";
131be306dacSThierry Reding				nvidia,function = "sata";
132be306dacSThierry Reding				nvidia,iddq = <0>;
133be306dacSThierry Reding			};
134be306dacSThierry Reding		};
135be306dacSThierry Reding	};
136