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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dhdp_v4_0.c27 #include "hdp/hdp_4_0_offset.h"
28 #include "hdp/hdp_4_0_sh_mask.h"
48 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); in hdp_v4_0_invalidate_hdp()
49 RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE); in hdp_v4_0_invalidate_hdp()
52 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); in hdp_v4_0_invalidate_hdp()
67 /* HDP SRAM errors are uncorrectable ones (i.e. fatal errors) */ in hdp_v4_0_query_ras_error_count()
68 err_data->ue_count += RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); in hdp_v4_0_query_ras_error_count()
77 WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0); in hdp_v4_0_reset_ras_error_count()
79 /*read back hdp ras counter to reset it to 0 */ in hdp_v4_0_reset_ras_error_count()
80 RREG32_SOC15(HDP, 0, mmHDP_EDC_CNT); in hdp_v4_0_reset_ras_error_count()
[all …]
H A Dhdp_v5_0.c26 #include "hdp/hdp_5_0_0_offset.h"
27 #include "hdp/hdp_5_0_0_sh_mask.h"
34 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); in hdp_v5_0_invalidate_hdp()
35 RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE); in hdp_v5_0_invalidate_hdp()
38 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); in hdp_v5_0_invalidate_hdp()
53 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in hdp_v5_0_update_mem_power_gating()
54 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in hdp_v5_0_update_mem_power_gating()
62 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_0_update_mem_power_gating()
64 /* HDP 5.0 doesn't support dynamic power mode switch, in hdp_v5_0_update_mem_power_gating()
82 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_0_update_mem_power_gating()
[all …]
H A Dhdp_v6_0.c26 #include "hdp/hdp_6_0_0_offset.h"
27 #include "hdp/hdp_6_0_0_sh_mask.h"
45 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1); in hdp_v6_0_update_clock_gating()
47 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v6_0_update_clock_gating()
48 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v6_0_update_clock_gating()
55 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
57 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
76 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v6_0_update_clock_gating()
112 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v6_0_update_clock_gating()
120 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL_V6_1, hdp_clk_cntl); in hdp_v6_0_update_clock_gating()
[all …]
H A Dhdp_v5_2.c26 #include "hdp/hdp_5_2_1_offset.h"
27 #include "hdp/hdp_5_2_1_sh_mask.h"
65 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_mem_power_gating()
66 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v5_2_update_mem_power_gating()
73 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_mem_power_gating()
92 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_2_update_mem_power_gating()
127 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v5_2_update_mem_power_gating()
136 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_mem_power_gating()
147 hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL); in hdp_v5_2_update_medium_grain_clock_gating()
167 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v5_2_update_medium_grain_clock_gating()
[all …]
H A Dhdp_v7_0.c26 #include "hdp/hdp_7_0_0_offset.h"
27 #include "hdp/hdp_7_0_0_sh_mask.h"
41 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL); in hdp_v7_0_update_clock_gating()
42 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v7_0_update_clock_gating()
48 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v7_0_update_clock_gating()
67 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v7_0_update_clock_gating()
103 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in hdp_v7_0_update_clock_gating()
110 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl); in hdp_v7_0_update_clock_gating()
119 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL); in hdp_v7_0_get_clockgating_state()
H A Dmmhub_v2_0.c44 [14][0] = "HDP",
58 [14][1] = "HDP",
75 [14][0] = "HDP",
91 [14][1] = "HDP",
103 [14][0] = "HDP",
115 [14][1] = "HDP",
H A Dmmhub_v3_3.c61 [24][0] = "HDP",
90 [24][1] = "HDP",
105 [24][0] = "HDP",
136 [24][1] = "HDP",
H A Dmmhub_v3_0_2.c44 [16][0] = "HDP",
65 [16][1] = "HDP",
H A Dmmhub_v3_0_1.c50 [22][0] = "HDP",
74 [22][1] = "HDP",
H A Dmmhub_v3_0.c44 [16][0] = "HDP",
65 [16][1] = "HDP",
H A Dmmhub_v2_3.c41 [27][0] = "HDP",
52 [27][1] = "HDP",
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dst,stm32-hdp.yaml5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-hdp.yaml#
14 STMicroelectronics's STM32 MPUs integrate a Hardware Debug Port (HDP).
20 - st,stm32mp131-hdp
21 - st,stm32mp151-hdp
22 - st,stm32mp251-hdp
31 "^hdp[0-7]-pins$":
38 pattern: '^HDP[0-7]$'
52 const: st,stm32mp131-hdp
55 "^hdp[0-7]-pins$":
92 const: st,stm32mp151-hdp
[all …]
/linux/drivers/video/fbdev/
H A Dcarminefb.c65 u32 hdp; member
108 .hdp = 640,
120 .hdp = 800,
134 if (car_modes[i].hdp == var->xres && in carmine_find_mode()
259 width = par->res->hdp * 4 / CARMINE_DISP_WIDTH_UNIT; in carmine_init_display_param()
276 window_size |= par->res->hdp; in carmine_init_display_param()
372 u32 hdp, vdp, htp, hsp, hsw, vtr, vsp, vsw; in set_display_parameters() local
378 hdp = par->res->hdp - 1; in set_display_parameters()
390 (hdp << CARMINE_DISP_HDB_SHIFT) | hdp); in set_display_parameters()
/linux/drivers/pinctrl/stm32/
H A DKconfig62 tristate "STMicroelectronics STM32 Hardware Debug Port (HDP) pin control"
72 It permits the observation of up to 16 signals per HDP line.
H A DMakefile14 obj-$(CONFIG_PINCTRL_STM32_HDP) += pinctrl-stm32-hdp.o
/linux/drivers/gpu/drm/bridge/
H A Daux-hpd-bridge.c96 * devm_drm_dp_hpd_bridge_add - register a HDP DisplayPort bridge
115 * drm_dp_hpd_bridge_register - allocate and register a HDP DisplayPort bridge
/linux/drivers/gpu/drm/radeon/
H A Dradeon_ring.c164 * @hdp_flush: Whether or not to perform an HDP cache flush
172 /* If we are emitting the HDP flush via the ring buffer, we need to in radeon_ring_commit()
182 /* If we are emitting the HDP flush via MMIO, we need to do it after in radeon_ring_commit()
196 * @hdp_flush: Whether or not to perform an HDP cache flush
H A Dcik_sdma.c161 * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
166 * Emit an hdp flush packet on the requested DMA ring.
212 /* flush HDP */ in cik_sdma_fence_ring_emit()
983 /* flush HDP */ in cik_dma_vm_flush()
H A Devergreen_dma.c52 /* flush HDP */ in evergreen_dma_fence_ring_emit()
/linux/drivers/net/wireless/quantenna/qtnfmac/pcie/
H A Dpearl_pcie_regs.h7 /* Pearl PCIe HDP registers */
96 /* PCIe HDP interrupt status definition */
/linux/drivers/net/ethernet/ti/
H A Ddavinci_cpdma.c110 void __iomem *hdp, *cp, *rxfree; member
393 chan_write(chan, hdp, desc_phys(pool, chan->head)); in cpdma_chan_on()
907 chan->hdp = ctlr->params.rxhdp + offset; in cpdma_chan_create()
915 chan->hdp = ctlr->params.txhdp + offset; in cpdma_chan_create()
997 chan_write(chan, hdp, desc_dma); in __cpdma_chan_submit()
1011 chan_write(chan, hdp, desc_dma); in __cpdma_chan_submit()
1260 chan_write(chan, hdp, desc_phys(pool, chan->head)); in __cpdma_chan_process()
/linux/fs/isofs/
H A Dinode.c623 struct hs_volume_descriptor *hdp; in isofs_fill_super() local
631 hdp = (struct hs_volume_descriptor *)bh->b_data; in isofs_fill_super()
635 * ISO CDs can match hdp->id==HS_STANDARD_ID as well. To ensure in isofs_fill_super()
673 if (strncmp (hdp->id, HS_STANDARD_ID, sizeof hdp->id) == 0) { in isofs_fill_super()
674 if (isonum_711(hdp->type) != ISO_VD_PRIMARY) in isofs_fill_super()
/linux/include/dt-bindings/clock/
H A Dstm32mp13-clks.h72 #define HDP 44 macro
H A Dstm32mp1-clks.h68 #define HDP 55 macro
/linux/drivers/clk/stm32/
H A Dclk-stm32mp13.c747 static struct clk_stm32_gate hdp = { variable
749 .hw.init = CLK_HW_INIT("hdp", "pclk3", &clk_stm32_gate_ops, 0),
1362 STM32_GATE_CFG(HDP, hdp, SECF_NONE),

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