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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi_i2c.c25 static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read) in fifo_transfer() argument
41 (hdmi->variant->ddc_fifo_thres_incl ? 0 : 1); in fifo_transfer()
50 if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, in fifo_transfer()
59 ioread8_rep(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
61 iowrite8_rep(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
64 regmap_field_force_write(hdmi->field_ddc_int_status, in fifo_transfer()
70 static int xfer_msg(struct sun4i_hdmi *hdmi, struct i2c_msg *msg) in xfer_msg() argument
76 if (hdmi->variant->ddc_fifo_has_dir) { in xfer_msg()
77 reg = readl(hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); in xfer_msg()
82 writel(reg, hdmi->base + SUN4I_HDMI_DDC_CTRL_REG); in xfer_msg()
[all …]
H A Dsun4i_hdmi_enc.c47 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); in sun4i_hdmi_write_infoframe() local
57 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i)); in sun4i_hdmi_write_infoframe()
66 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); in sun4i_hdmi_disable() local
69 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n"); in sun4i_hdmi_disable()
71 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); in sun4i_hdmi_disable()
73 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); in sun4i_hdmi_disable()
75 clk_disable_unprepare(hdmi->tmds_clk); in sun4i_hdmi_disable()
82 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); in sun4i_hdmi_enable() local
83 struct drm_connector *connector = &hdmi->connector; in sun4i_hdmi_enable()
87 unsigned long long tmds_rate = conn_state->hdmi.tmds_char_rate; in sun4i_hdmi_enable()
[all …]
H A Dsun8i_dw_hdmi.c22 struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder); in sun8i_dw_hdmi_encoder_mode_set() local
24 clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000); in sun8i_dw_hdmi_encoder_mode_set()
33 sun8i_dw_hdmi_mode_valid_a83t(struct dw_hdmi *hdmi, void *data, in sun8i_dw_hdmi_mode_valid_a83t() argument
44 sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data, in sun8i_dw_hdmi_mode_valid_h6() argument
104 struct sun8i_dw_hdmi *hdmi; in sun8i_dw_hdmi_bind() local
110 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); in sun8i_dw_hdmi_bind()
111 if (!hdmi) in sun8i_dw_hdmi_bind()
114 plat_data = &hdmi->plat_data; in sun8i_dw_hdmi_bind()
115 hdmi->dev = &pdev->dev; in sun8i_dw_hdmi_bind()
116 encoder = &hdmi->encoder; in sun8i_dw_hdmi_bind()
[all …]
H A Dsun8i_hdmi_phy.c142 static int sun8i_a83t_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, in sun8i_a83t_hdmi_phy_config() argument
156 dw_hdmi_phy_gen2_txpwron(hdmi, 0); in sun8i_a83t_hdmi_phy_config()
157 dw_hdmi_phy_gen2_pddq(hdmi, 1); in sun8i_a83t_hdmi_phy_config()
159 dw_hdmi_phy_gen2_reset(hdmi); in sun8i_a83t_hdmi_phy_config()
161 dw_hdmi_phy_gen2_pddq(hdmi, 0); in sun8i_a83t_hdmi_phy_config()
163 dw_hdmi_phy_i2c_set_addr(hdmi, I2C_ADDR); in sun8i_a83t_hdmi_phy_config()
166 * Values are taken from BSP HDMI driver. Although AW didn't in sun8i_a83t_hdmi_phy_config()
171 dw_hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06); in sun8i_a83t_hdmi_phy_config()
172 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x15); in sun8i_a83t_hdmi_phy_config()
173 dw_hdmi_phy_i2c_write(hdmi, 0x08da, 0x10); in sun8i_a83t_hdmi_phy_config()
[all …]
H A Dsun4i_hdmi_tmds_clk.c16 struct sun4i_hdmi *hdmi; member
78 * clocked from it, and to have the same rate than our HDMI in sun4i_tmds_determine_rate()
131 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); in sun4i_tmds_recalc_rate()
135 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); in sun4i_tmds_recalc_rate()
154 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); in sun4i_tmds_set_rate()
158 writel(reg, tmds->hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); in sun4i_tmds_set_rate()
160 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); in sun4i_tmds_set_rate()
163 tmds->hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); in sun4i_tmds_set_rate()
173 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG); in sun4i_tmds_get_parent()
186 reg = readl(tmds->hdmi->base + SUN4I_HDMI_PLL_DBG0_REG); in sun4i_tmds_set_parent()
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/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi5.c3 * HDMI driver for OMAP5
14 #define DSS_SUBSYS_NAME "HDMI"
32 #include <sound/omap-hdmi-audio.h>
38 static struct omap_hdmi hdmi; variable
46 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
59 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
88 v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL); in hdmi_irq_handler()
91 hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v); in hdmi_irq_handler()
98 REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); in hdmi_irq_handler()
113 if (hdmi.vdda_reg != NULL) in hdmi_init_regulator()
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H A Dhdmi4.c3 * HDMI interface DSS driver for TI's OMAP4 family of SoCs.
9 #define DSS_SUBSYS_NAME "HDMI"
27 #include <sound/omap-hdmi-audio.h>
32 #include "hdmi.h"
34 static struct omap_hdmi hdmi; variable
42 r = pm_runtime_resume_and_get(&hdmi.pdev->dev); in hdmi_runtime_get()
55 r = pm_runtime_put_sync(&hdmi.pdev->dev); in hdmi_runtime_put()
94 if (hdmi.vdda_reg != NULL) in hdmi_init_regulator()
97 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); in hdmi_init_regulator()
105 hdmi.vdda_reg = reg; in hdmi_init_regulator()
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/linux/drivers/gpu/drm/rockchip/
H A Ddw_hdmi_qp-rockchip.c92 struct dw_hdmi_qp *hdmi; member
101 void (*io_init)(struct rockchip_hdmi_qp *hdmi);
115 struct rockchip_hdmi_qp *hdmi = to_rockchip_hdmi_qp(encoder); in dw_hdmi_qp_rockchip_encoder_enable() local
120 gpiod_set_value(hdmi->enable_gpio, 1); in dw_hdmi_qp_rockchip_encoder_enable()
132 phy_set_bus_width(hdmi->phy, div_u64(rate, 100)); in dw_hdmi_qp_rockchip_encoder_enable()
157 struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; in dw_hdmi_qp_rk3588_phy_init() local
159 return phy_power_on(hdmi->phy); in dw_hdmi_qp_rk3588_phy_init()
165 struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; in dw_hdmi_qp_rk3588_phy_disable() local
167 phy_power_off(hdmi->phy); in dw_hdmi_qp_rk3588_phy_disable()
173 struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data; in dw_hdmi_qp_rk3588_read_hpd() local
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/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_hdcp.c5 #include "hdmi.h"
21 /* QFPROM Registers for HDMI/HDCP */
49 struct hdmi *hdmi; member
78 static int msm_hdmi_ddc_read(struct hdmi *hdmi, u16 addr, u8 offset, in msm_hdmi_ddc_read() argument
99 rc = i2c_transfer(hdmi->i2c, msgs, 2); in msm_hdmi_ddc_read()
116 static int msm_hdmi_ddc_write(struct hdmi *hdmi, u16 addr, u8 offset, in msm_hdmi_ddc_write() argument
141 rc = i2c_transfer(hdmi->i2c, msgs, 1); in msm_hdmi_ddc_write()
159 struct hdmi *hdmi = hdcp_ctrl->hdmi; in msm_hdmi_hdcp_scm_wr() local
167 phy_addr = (u32)hdmi->mmio_phy_addr; in msm_hdmi_hdcp_scm_wr()
190 hdmi_write(hdmi, preg[i], pdata[i]); in msm_hdmi_hdcp_scm_wr()
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/linux/drivers/media/i2c/adv748x/
H A Dadv748x-hdmi.c3 * Driver for Analog Devices ADV748X HDMI receiver and Component Processor (CP)
21 * HDMI and CP
90 static void adv748x_hdmi_fill_format(struct adv748x_hdmi *hdmi, in adv748x_hdmi_fill_format() argument
96 fmt->field = hdmi->timings.bt.interlaced ? in adv748x_hdmi_fill_format()
102 fmt->width = hdmi->timings.bt.width; in adv748x_hdmi_fill_format()
103 fmt->height = hdmi->timings.bt.height; in adv748x_hdmi_fill_format()
145 * HDMI CP uses a Data Enable synchronisation timing reference
220 struct adv748x_hdmi *hdmi = adv748x_sd_to_hdmi(sd); in adv748x_hdmi_s_dv_timings() local
221 struct adv748x_state *state = adv748x_hdmi_to_state(hdmi); in adv748x_hdmi_s_dv_timings()
227 if (v4l2_match_dv_timings(&hdmi->timings, timings, 0, false)) in adv748x_hdmi_s_dv_timings()
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/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos-hdmi.yaml4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
7 title: Samsung Exynos SoC HDMI
18 - samsung,exynos4210-hdmi
19 - samsung,exynos4212-hdmi
20 - samsung,exynos5420-hdmi
21 - samsung,exynos5433-hdmi
34 Phandle to the HDMI DDC node.
36 hdmi-en-supply:
38 Provides voltage source for DCC lines available on HDMI connector. When
40 HPD (hot plug detect) line, what causes HDMI block to stay turned off.
[all …]
/linux/drivers/gpu/drm/imx/ipuv3/
H A Ddw_hdmi-imx.c4 * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
31 struct imx_hdmi *hdmi; member
37 struct dw_hdmi *hdmi; member
43 return container_of(e, struct imx_hdmi_encoder, encoder)->hdmi; in enc_to_imx_hdmi()
112 struct imx_hdmi *hdmi = enc_to_imx_hdmi(encoder); in dw_hdmi_imx_encoder_enable() local
113 int mux = drm_of_encoder_active_port_id(hdmi->dev->of_node, encoder); in dw_hdmi_imx_encoder_enable()
115 regmap_update_bits(hdmi->regmap, IOMUXC_GPR3, in dw_hdmi_imx_encoder_enable()
139 imx6q_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, in imx6q_hdmi_mode_valid() argument
153 imx6dl_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, in imx6dl_hdmi_mode_valid() argument
181 { .compatible = "fsl,imx6q-hdmi",
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/linux/drivers/gpu/drm/bridge/imx/
H A Dimx8mp-hdmi-tx.c25 struct imx8mp_hdmi *hdmi = (struct imx8mp_hdmi *)data; in imx8mp_hdmi_mode_valid() local
34 round_rate = clk_round_rate(hdmi->pixclk, mode->clock * 1000); in imx8mp_hdmi_mode_valid()
35 /* imx8mp's pixel clock generator (fsl-samsung-hdmi) cannot generate in imx8mp_hdmi_mode_valid()
63 static void im8mp_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) in im8mp_hdmi_phy_setup_hpd() argument
69 dw_hdmi_phy_gen1_reset(hdmi); in im8mp_hdmi_phy_setup_hpd()
71 dw_hdmi_phy_setup_hpd(hdmi, data); in im8mp_hdmi_phy_setup_hpd()
86 struct imx8mp_hdmi *hdmi; in imx8mp_dw_hdmi_probe() local
88 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); in imx8mp_dw_hdmi_probe()
89 if (!hdmi) in imx8mp_dw_hdmi_probe()
92 plat_data = &hdmi->plat_data; in imx8mp_dw_hdmi_probe()
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dw-hdmi.yaml4 $id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
7 title: Renesas R-Car DWC HDMI TX Encoder
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: synopsys,dw-hdmi.yaml#
23 - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
24 - renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX
25 - renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX
26 - renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX
27 - renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX
28 - renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX
[all …]
/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-dai-tdm.c347 {"HDMI_CH0_MUX", "CH0", "HDMI"},
348 {"HDMI_CH0_MUX", "CH1", "HDMI"},
349 {"HDMI_CH0_MUX", "CH2", "HDMI"},
350 {"HDMI_CH0_MUX", "CH3", "HDMI"},
351 {"HDMI_CH0_MUX", "CH4", "HDMI"},
352 {"HDMI_CH0_MUX", "CH5", "HDMI"},
353 {"HDMI_CH0_MUX", "CH6", "HDMI"},
354 {"HDMI_CH0_MUX", "CH7", "HDMI"},
356 {"HDMI_CH1_MUX", "CH0", "HDMI"},
357 {"HDMI_CH1_MUX", "CH1", "HDMI"},
[all …]
/linux/drivers/gpu/drm/sti/
H A Dsti_hdmi_tx3g4c28phy.c70 * sti_hdmi_tx3g4c28phy_start - Start hdmi phy macro cell tx3g4c28
72 * @hdmi: pointer on the hdmi internal structure
76 static bool sti_hdmi_tx3g4c28phy_start(struct sti_hdmi *hdmi) in sti_hdmi_tx3g4c28phy_start() argument
78 u32 ckpxpll = hdmi->mode.clock * 1000; in sti_hdmi_tx3g4c28phy_start()
116 hdmi->event_received = false; in sti_hdmi_tx3g4c28phy_start()
118 hdmi_write(hdmi, (pllctrl | PLL_CFG_EN), HDMI_SRZ_PLL_CFG); in sti_hdmi_tx3g4c28phy_start()
121 wait_event_interruptible_timeout(hdmi->wait_event, in sti_hdmi_tx3g4c28phy_start()
122 hdmi->event_received == true, in sti_hdmi_tx3g4c28phy_start()
126 if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK) == 0) { in sti_hdmi_tx3g4c28phy_start()
127 DRM_ERROR("hdmi phy pll not locked\n"); in sti_hdmi_tx3g4c28phy_start()
[all …]
H A Dsti_hdmi.h10 #include <linux/hdmi.h>
25 bool (*start)(struct sti_hdmi *hdmi);
26 void (*stop)(struct sti_hdmi *hdmi);
39 * STI hdmi structure
44 * @regs: hdmi register
46 * @clk_pix: hdmi pixel clock
47 * @clk_tmds: hdmi tmds clock
48 * @clk_phy: hdmi phy clock
49 * @clk_audio: hdmi audio clock
50 * @irq: hdmi interrupt number
[all …]
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-dai-tdm.c395 {"HDMI_CH0_MUX", "CH0", "HDMI"},
396 {"HDMI_CH0_MUX", "CH1", "HDMI"},
397 {"HDMI_CH0_MUX", "CH2", "HDMI"},
398 {"HDMI_CH0_MUX", "CH3", "HDMI"},
399 {"HDMI_CH0_MUX", "CH4", "HDMI"},
400 {"HDMI_CH0_MUX", "CH5", "HDMI"},
401 {"HDMI_CH0_MUX", "CH6", "HDMI"},
402 {"HDMI_CH0_MUX", "CH7", "HDMI"},
404 {"HDMI_CH1_MUX", "CH0", "HDMI"},
405 {"HDMI_CH1_MUX", "CH1", "HDMI"},
[all …]
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi-i2s-audio.c3 * dw-hdmi-i2s-audio.c
15 #include <sound/hdmi-codec.h>
17 #include "dw-hdmi.h"
18 #include "dw-hdmi-audio.h"
20 #define DRIVER_NAME "dw-hdmi-i2s-audio"
25 struct dw_hdmi *hdmi = audio->hdmi; in hdmi_write() local
27 audio->write(hdmi, val, offset); in hdmi_write()
32 struct dw_hdmi *hdmi = audio->hdmi; in hdmi_read() local
34 return audio->read(hdmi, offset); in hdmi_read()
42 struct dw_hdmi *hdmi = audio->hdmi; in dw_hdmi_i2s_hw_params() local
[all …]
/linux/sound/pci/oxygen/
H A Dxonar_hdmi.c3 * helper functions for HDMI models (Xonar HDAV1.3/HDAV1.3 Slim)
37 struct xonar_hdmi *hdmi) in xonar_hdmi_init_commands() argument
46 hdmi_write_command(chip, 0x54, 5, hdmi->params); in xonar_hdmi_init_commands()
49 void xonar_hdmi_init(struct oxygen *chip, struct xonar_hdmi *hdmi) in xonar_hdmi_init() argument
51 hdmi->params[1] = IEC958_AES3_CON_FS_48000; in xonar_hdmi_init()
52 hdmi->params[4] = 1; in xonar_hdmi_init()
53 xonar_hdmi_init_commands(chip, hdmi); in xonar_hdmi_init()
63 void xonar_hdmi_resume(struct oxygen *chip, struct xonar_hdmi *hdmi) in xonar_hdmi_resume() argument
65 xonar_hdmi_init_commands(chip, hdmi); in xonar_hdmi_resume()
80 void xonar_set_hdmi_params(struct oxygen *chip, struct xonar_hdmi *hdmi, in xonar_set_hdmi_params() argument
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-boneblack.dts10 #include "am335x-boneblack-hdmi.dtsi"
50 "[hdmi cec]",
92 "[hdmi irq]",
94 "[hdmi audio]",
109 "P8_45 [hdmi]",
110 "P8_46 [hdmi]",
111 "P8_43 [hdmi]",
112 "P8_44 [hdmi]",
113 "P8_41 [hdmi]",
114 "P8_42 [hdmi]",
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-hdmi.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
7 title: NVIDIA Tegra HDMI Output Encoder
15 pattern: "^hdmi@[0-9a-f]+$"
20 - nvidia,tegra20-hdmi
21 - nvidia,tegra30-hdmi
22 - nvidia,tegra114-hdmi
23 - nvidia,tegra124-hdmi
26 - const: nvidia,tegra132-hdmi
27 - const: nvidia,tegra124-hdmi
42 - const: hdmi
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun4i-a10-hdmi.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml#
7 title: Allwinner A10 HDMI Controller
10 The HDMI Encoder supports the HDMI video and audio outputs, and does
20 - const: allwinner,sun4i-a10-hdmi
21 - const: allwinner,sun5i-a10s-hdmi
22 - const: allwinner,sun6i-a31-hdmi
24 - const: allwinner,sun7i-a20-hdmi
25 - const: allwinner,sun5i-a10s-hdmi
36 - description: The HDMI interface clock
37 - description: The HDMI module clock
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dimx-audio-hdmi.yaml4 $id: http://devicetree.org/schemas/sound/imx-audio-hdmi.yaml#
7 title: NXP i.MX audio complex with HDMI
15 - fsl,imx-audio-hdmi
26 hdmi-out:
30 of HDMI will be enabled, indicating there's a physical HDMI out
32 block, such as an HDMI encoder or display-controller.
34 hdmi-in:
38 HDMI will be enabled, indicating there is a physical HDMI in
50 sound-hdmi {
51 compatible = "fsl,imx-audio-hdmi";
[all …]
/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,dw-hdmi.yaml4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
7 title: Rockchip DWC HDMI TX Encoder
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
23 - rockchip,rk3228-dw-hdmi
24 - rockchip,rk3288-dw-hdmi
25 - rockchip,rk3328-dw-hdmi
26 - rockchip,rk3399-dw-hdmi
27 - rockchip,rk3568-dw-hdmi
50 - description: The HDMI CEC controller main clock
[all …]

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