Lines Matching full:hdmi
10 #include <linux/hdmi.h>
29 #include <sound/hdmi-codec.h>
31 #include "dw-hdmi-qp.h"
46 * the recommended N values specified in the Audio chapter of the HDMI
93 /* For 297 MHz+ HDMI spec have some other rule for setting N */
102 * These are the CTS values as recommended in the Audio chapter of the HDMI
150 static void dw_hdmi_qp_write(struct dw_hdmi_qp *hdmi, unsigned int val,
153 regmap_write(hdmi->regm, offset, val);
156 static unsigned int dw_hdmi_qp_read(struct dw_hdmi_qp *hdmi, int offset)
160 regmap_read(hdmi->regm, offset, &val);
165 static void dw_hdmi_qp_mod(struct dw_hdmi_qp *hdmi, unsigned int data,
168 regmap_update_bits(hdmi->regm, reg, mask, data);
176 static void dw_hdmi_qp_set_cts_n(struct dw_hdmi_qp *hdmi, unsigned int cts,
180 dw_hdmi_qp_mod(hdmi, n, AUDPKT_ACR_N_VALUE, AUDPKT_ACR_CONTROL0);
184 dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_EN, AUDPKT_ACR_CTS_OVR_EN_MSK,
187 dw_hdmi_qp_mod(hdmi, 0, AUDPKT_ACR_CTS_OVR_EN_MSK,
190 dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_VAL(cts), AUDPKT_ACR_CTS_OVR_VAL_MSK,
194 static int dw_hdmi_qp_match_tmds_n_table(struct dw_hdmi_qp *hdmi,
235 static unsigned int dw_hdmi_qp_compute_n(struct dw_hdmi_qp *hdmi,
272 static unsigned int dw_hdmi_qp_find_n(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk,
275 int n = dw_hdmi_qp_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
280 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
283 return dw_hdmi_qp_compute_n(hdmi, pixel_clk, sample_rate);
286 static unsigned int dw_hdmi_qp_find_cts(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk,
318 static void dw_hdmi_qp_set_audio_interface(struct dw_hdmi_qp *hdmi,
325 dw_hdmi_qp_write(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWINIT_P, GLOBAL_SWRESET_REQUEST);
328 dw_hdmi_qp_mod(hdmi, 0,
333 dw_hdmi_qp_write(hdmi, AUDIO_FIFO_CLR_P, AUDIO_INTERFACE_CONTROL0);
336 dw_hdmi_qp_mod(hdmi, AUD_IF_I2S, AUD_IF_SEL_MSK, AUDIO_INTERFACE_CONFIG0);
354 dw_hdmi_qp_mod(hdmi, conf0, I2S_LINES_EN_MSK, AUDIO_INTERFACE_CONFIG0);
370 dw_hdmi_qp_mod(hdmi, conf0, I2S_BPCUV_RCV_MSK | AUD_FORMAT_MSK,
374 dw_hdmi_qp_mod(hdmi, AUD_FIFO_INIT_ON_OVF_EN, AUD_FIFO_INIT_ON_OVF_MSK,
386 static void dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp *hdmi,
411 if ((dw_hdmi_qp_read(hdmi, AUDIO_INTERFACE_CONFIG0) & GENMASK(25, 24)) == AUD_HBR) {
417 dw_hdmi_qp_write(hdmi, channel_status[0] | (channel_status[1] << 8),
420 regmap_bulk_write(hdmi->regm, AUDPKT_CHSTATUS_OVR1, &channel_status[3], 1);
423 dw_hdmi_qp_mod(hdmi, 0,
427 dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN,
432 static void dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp *hdmi, unsigned long long tmds_char_rate,
437 n = dw_hdmi_qp_find_n(hdmi, tmds_char_rate, sample_rate);
438 cts = dw_hdmi_qp_find_cts(hdmi, tmds_char_rate, sample_rate);
440 dw_hdmi_qp_set_cts_n(hdmi, cts, n);
446 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
448 if (hdmi->tmds_char_rate)
449 dw_hdmi_qp_mod(hdmi, 0, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE);
459 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
462 if (!hdmi->tmds_char_rate)
466 dev_err(hdmi->dev, "unsupported clock settings\n");
473 dw_hdmi_qp_set_audio_interface(hdmi, fmt, hparms);
474 dw_hdmi_qp_set_sample_rate(hdmi, hdmi->tmds_char_rate, hparms->sample_rate);
475 dw_hdmi_qp_set_channel_status(hdmi, hparms->iec.status, ref2stream);
481 static void dw_hdmi_qp_audio_disable_regs(struct dw_hdmi_qp *hdmi)
490 dw_hdmi_qp_mod(hdmi, I2S_BPCUV_RCV_DIS, I2S_BPCUV_RCV_MSK,
492 dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN,
496 dw_hdmi_qp_mod(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE,
503 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
507 if (hdmi->tmds_char_rate)
508 dw_hdmi_qp_audio_disable_regs(hdmi);
511 static int dw_hdmi_qp_i2c_read(struct dw_hdmi_qp *hdmi,
514 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
518 dev_dbg(hdmi->dev, "set read register address to 0\n");
526 dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
530 dw_hdmi_qp_mod(hdmi, I2CM_EXT_READ, I2CM_WR_MASK,
533 dw_hdmi_qp_mod(hdmi, I2CM_FM_READ, I2CM_WR_MASK,
538 dev_err(hdmi->dev, "i2c read timed out\n");
539 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
545 dev_err(hdmi->dev, "i2c read error\n");
546 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
550 *buf++ = dw_hdmi_qp_read(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff;
551 dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
559 static int dw_hdmi_qp_i2c_write(struct dw_hdmi_qp *hdmi,
562 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
576 dw_hdmi_qp_write(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3);
577 dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
579 dw_hdmi_qp_mod(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK,
584 dev_err(hdmi->dev, "i2c write time out!\n");
585 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
591 dev_err(hdmi->dev, "i2c write nack!\n");
592 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
596 dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
605 struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap);
606 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
621 dev_err(hdmi->dev,
631 dw_hdmi_qp_mod(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
639 dw_hdmi_qp_mod(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0);
650 dw_hdmi_qp_mod(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR,
652 dw_hdmi_qp_mod(hdmi, *msgs[i].buf << 7, I2CM_SEG_PTR,
656 ret = dw_hdmi_qp_i2c_read(hdmi, msgs[i].buf,
659 ret = dw_hdmi_qp_i2c_write(hdmi, msgs[i].buf,
670 dw_hdmi_qp_mod(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N,
686 static struct i2c_adapter *dw_hdmi_qp_i2c_adapter(struct dw_hdmi_qp *hdmi)
692 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
701 adap->dev.parent = hdmi->dev;
703 strscpy(adap->name, "DesignWare HDMI QP", sizeof(adap->name));
705 i2c_set_adapdata(adap, hdmi);
707 ret = devm_i2c_add_adapter(hdmi->dev, adap);
709 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
710 devm_kfree(hdmi->dev, i2c);
714 hdmi->i2c = i2c;
715 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
720 static int dw_hdmi_qp_config_avi_infoframe(struct dw_hdmi_qp *hdmi,
726 dev_err(hdmi->dev, "failed to configure avi infoframe\n");
731 * DW HDMI QP IP uses a different byte format from standard AVI info
735 dw_hdmi_qp_write(hdmi, val, PKT_AVI_CONTENTS0);
746 dw_hdmi_qp_write(hdmi, val, PKT_AVI_CONTENTS1 + i * 4);
749 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1);
751 dw_hdmi_qp_mod(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN,
757 static int dw_hdmi_qp_config_drm_infoframe(struct dw_hdmi_qp *hdmi,
763 dev_err(hdmi->dev, "failed to configure drm infoframe\n");
767 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
770 dw_hdmi_qp_write(hdmi, val, PKT_DRMI_CONTENTS0);
778 dw_hdmi_qp_write(hdmi, val,
782 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_FIELDRATE, PKTSCHED_PKT_CONFIG1);
783 dw_hdmi_qp_mod(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN,
796 static int dw_hdmi_qp_config_audio_infoframe(struct dw_hdmi_qp *hdmi,
812 * AUDI_CONTENTS0 default value defined by HDMI specification,
818 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS0, &header_bytes, 1);
819 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS1, &buffer[3], 1);
820 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS2, &buffer[4], 1);
823 dw_hdmi_qp_mod(hdmi,
829 dw_hdmi_qp_mod(hdmi, PKTSCHED_AUDS_TX_EN, PKTSCHED_AUDS_TX_EN, PKTSCHED_PKT_EN);
837 struct dw_hdmi_qp *hdmi = bridge->driver_private;
851 dev_dbg(hdmi->dev, "%s mode=HDMI rate=%llu\n",
852 __func__, conn_state->hdmi.tmds_char_rate);
854 hdmi->tmds_char_rate = conn_state->hdmi.tmds_char_rate;
856 dev_dbg(hdmi->dev, "%s mode=DVI\n", __func__);
860 hdmi->phy.ops->init(hdmi, hdmi->phy.data);
862 dw_hdmi_qp_mod(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0);
863 dw_hdmi_qp_mod(hdmi, op_mode, OPMODE_DVI, LINK_CONFIG0);
871 struct dw_hdmi_qp *hdmi = bridge->driver_private;
873 hdmi->tmds_char_rate = 0;
875 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
881 struct dw_hdmi_qp *hdmi = bridge->driver_private;
883 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
890 struct dw_hdmi_qp *hdmi = bridge->driver_private;
895 dev_dbg(hdmi->dev, "failed to get edid\n");
905 struct dw_hdmi_qp *hdmi = bridge->driver_private;
908 dev_dbg(hdmi->dev, "Unsupported TMDS char rate: %lld\n", rate);
918 struct dw_hdmi_qp *hdmi = bridge->driver_private;
922 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN,
927 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
931 dw_hdmi_qp_mod(hdmi, 0,
938 dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type);
948 struct dw_hdmi_qp *hdmi = bridge->driver_private;
954 return dw_hdmi_qp_config_avi_infoframe(hdmi, buffer, len);
957 return dw_hdmi_qp_config_drm_infoframe(hdmi, buffer, len);
960 return dw_hdmi_qp_config_audio_infoframe(hdmi, buffer, len);
963 dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type);
986 struct dw_hdmi_qp *hdmi = dev_id;
987 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
990 stat = dw_hdmi_qp_read(hdmi, MAINUNIT_1_INT_STATUS);
996 dw_hdmi_qp_write(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR);
1013 static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *hdmi)
1015 dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N);
1016 dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N);
1017 dw_hdmi_qp_write(hdmi, 428571429, TIMER_BASE_CONFIG0);
1020 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
1022 dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0);
1024 dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0);
1027 dw_hdmi_qp_write(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR,
1030 if (hdmi->phy.ops->setup_hpd)
1031 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
1039 struct dw_hdmi_qp *hdmi;
1049 hdmi = devm_drm_bridge_alloc(dev, struct dw_hdmi_qp, bridge,
1051 if (IS_ERR(hdmi))
1052 return ERR_CAST(hdmi);
1054 hdmi->dev = dev;
1060 hdmi->regm = devm_regmap_init_mmio(dev, regs, &dw_hdmi_qp_regmap_config);
1061 if (IS_ERR(hdmi->regm)) {
1063 return ERR_CAST(hdmi->regm);
1066 hdmi->phy.ops = plat_data->phy_ops;
1067 hdmi->phy.data = plat_data->phy_data;
1069 dw_hdmi_qp_init_hw(hdmi);
1073 IRQF_SHARED, dev_name(dev), hdmi);
1077 hdmi->bridge.driver_private = hdmi;
1078 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT |
1083 hdmi->bridge.of_node = pdev->dev.of_node;
1084 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1085 hdmi->bridge.vendor = "Synopsys";
1086 hdmi->bridge.product = "DW HDMI QP TX";
1088 hdmi->bridge.ddc = dw_hdmi_qp_i2c_adapter(hdmi);
1089 if (IS_ERR(hdmi->bridge.ddc))
1090 return ERR_CAST(hdmi->bridge.ddc);
1092 hdmi->bridge.hdmi_audio_max_i2s_playback_channels = 8;
1093 hdmi->bridge.hdmi_audio_dev = dev;
1094 hdmi->bridge.hdmi_audio_dai_port = 1;
1096 ret = devm_drm_bridge_add(dev, &hdmi->bridge);
1100 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL,
1105 return hdmi;
1109 void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi)
1111 dw_hdmi_qp_init_hw(hdmi);
1117 MODULE_DESCRIPTION("DW HDMI QP transmitter library");