Lines Matching full:hdmi
3 * MediaTek HDMI v2 IP driver
57 [MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI] = "hdmi-split",
60 static inline void mtk_hdmi_v2_hwirq_disable(struct mtk_hdmi *hdmi) in mtk_hdmi_v2_hwirq_disable() argument
62 regmap_write(hdmi->regs, TOP_INT_ENABLE00, 0); in mtk_hdmi_v2_hwirq_disable()
63 regmap_write(hdmi->regs, TOP_INT_ENABLE01, 0); in mtk_hdmi_v2_hwirq_disable()
66 static inline void mtk_hdmi_v2_enable_hpd_pord_irq(struct mtk_hdmi *hdmi, bool enable) in mtk_hdmi_v2_enable_hpd_pord_irq() argument
69 regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS); in mtk_hdmi_v2_enable_hpd_pord_irq()
71 regmap_clear_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS); in mtk_hdmi_v2_enable_hpd_pord_irq()
74 static inline void mtk_hdmi_v2_set_sw_hpd(struct mtk_hdmi *hdmi, bool enable) in mtk_hdmi_v2_set_sw_hpd() argument
77 regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD); in mtk_hdmi_v2_set_sw_hpd()
78 regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR); in mtk_hdmi_v2_set_sw_hpd()
79 regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW); in mtk_hdmi_v2_set_sw_hpd()
81 regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR); in mtk_hdmi_v2_set_sw_hpd()
82 regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW); in mtk_hdmi_v2_set_sw_hpd()
83 regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD); in mtk_hdmi_v2_set_sw_hpd()
87 static inline void mtk_hdmi_v2_enable_scrambling(struct mtk_hdmi *hdmi, bool enable) in mtk_hdmi_v2_enable_scrambling() argument
89 struct drm_scdc *scdc = &hdmi->curr_conn->display_info.hdmi.scdc; in mtk_hdmi_v2_enable_scrambling()
92 regmap_set_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON); in mtk_hdmi_v2_enable_scrambling()
94 regmap_clear_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON); in mtk_hdmi_v2_enable_scrambling()
98 drm_scdc_set_scrambling(hdmi->curr_conn, enable); in mtk_hdmi_v2_enable_scrambling()
99 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, enable); in mtk_hdmi_v2_enable_scrambling()
103 static void mtk_hdmi_v2_hw_vid_mute(struct mtk_hdmi *hdmi, bool enable) in mtk_hdmi_v2_hw_vid_mute() argument
107 regmap_set_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN); in mtk_hdmi_v2_hw_vid_mute()
109 regmap_clear_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN); in mtk_hdmi_v2_hw_vid_mute()
112 static void mtk_hdmi_v2_hw_aud_mute(struct mtk_hdmi *hdmi, bool enable) in mtk_hdmi_v2_hw_aud_mute() argument
117 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_MUTE_FIFO_EN); in mtk_hdmi_v2_hw_aud_mute()
121 regmap_read(hdmi->regs, AIP_CTRL, &aip); in mtk_hdmi_v2_hw_aud_mute()
127 regmap_update_bits(hdmi->regs, AIP_TXCTRL, val, val); in mtk_hdmi_v2_hw_aud_mute()
130 static void mtk_hdmi_v2_hw_reset(struct mtk_hdmi *hdmi) in mtk_hdmi_v2_hw_reset() argument
132 regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB); in mtk_hdmi_v2_hw_reset()
134 regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB); in mtk_hdmi_v2_hw_reset()
148 static void mtk_hdmi_v2_hw_write_audio_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer) in mtk_hdmi_v2_hw_write_audio_infoframe() argument
150 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR); in mtk_hdmi_v2_hw_write_audio_infoframe()
151 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN); in mtk_hdmi_v2_hw_write_audio_infoframe()
153 regmap_write(hdmi->regs, TOP_AIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3)); in mtk_hdmi_v2_hw_write_audio_infoframe()
154 regmap_write(hdmi->regs, TOP_AIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 3)); in mtk_hdmi_v2_hw_write_audio_infoframe()
155 regmap_write(hdmi->regs, TOP_AIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 2)); in mtk_hdmi_v2_hw_write_audio_infoframe()
156 regmap_write(hdmi->regs, TOP_AIF_PKT02, 0); in mtk_hdmi_v2_hw_write_audio_infoframe()
157 regmap_write(hdmi->regs, TOP_AIF_PKT03, 0); in mtk_hdmi_v2_hw_write_audio_infoframe()
159 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN); in mtk_hdmi_v2_hw_write_audio_infoframe()
160 regmap_set_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR); in mtk_hdmi_v2_hw_write_audio_infoframe()
163 static void mtk_hdmi_v2_hw_write_avi_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer) in mtk_hdmi_v2_hw_write_avi_infoframe() argument
165 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN); in mtk_hdmi_v2_hw_write_avi_infoframe()
166 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN); in mtk_hdmi_v2_hw_write_avi_infoframe()
168 regmap_write(hdmi->regs, TOP_AVI_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3)); in mtk_hdmi_v2_hw_write_avi_infoframe()
169 regmap_write(hdmi->regs, TOP_AVI_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4)); in mtk_hdmi_v2_hw_write_avi_infoframe()
170 regmap_write(hdmi->regs, TOP_AVI_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 3)); in mtk_hdmi_v2_hw_write_avi_infoframe()
171 regmap_write(hdmi->regs, TOP_AVI_PKT02, mtk_hdmi_v2_format_hw_packet(&buffer[10], 4)); in mtk_hdmi_v2_hw_write_avi_infoframe()
172 regmap_write(hdmi->regs, TOP_AVI_PKT03, mtk_hdmi_v2_format_hw_packet(&buffer[14], 3)); in mtk_hdmi_v2_hw_write_avi_infoframe()
173 regmap_write(hdmi->regs, TOP_AVI_PKT04, 0); in mtk_hdmi_v2_hw_write_avi_infoframe()
174 regmap_write(hdmi->regs, TOP_AVI_PKT05, 0); in mtk_hdmi_v2_hw_write_avi_infoframe()
176 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN); in mtk_hdmi_v2_hw_write_avi_infoframe()
177 regmap_set_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN); in mtk_hdmi_v2_hw_write_avi_infoframe()
180 static void mtk_hdmi_v2_hw_write_spd_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer) in mtk_hdmi_v2_hw_write_spd_infoframe() argument
182 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN); in mtk_hdmi_v2_hw_write_spd_infoframe()
183 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN); in mtk_hdmi_v2_hw_write_spd_infoframe()
185 regmap_write(hdmi->regs, TOP_SPDIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3)); in mtk_hdmi_v2_hw_write_spd_infoframe()
186 regmap_write(hdmi->regs, TOP_SPDIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4)); in mtk_hdmi_v2_hw_write_spd_infoframe()
187 regmap_write(hdmi->regs, TOP_SPDIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 3)); in mtk_hdmi_v2_hw_write_spd_infoframe()
188 regmap_write(hdmi->regs, TOP_SPDIF_PKT02, mtk_hdmi_v2_format_hw_packet(&buffer[10], 4)); in mtk_hdmi_v2_hw_write_spd_infoframe()
189 regmap_write(hdmi->regs, TOP_SPDIF_PKT03, mtk_hdmi_v2_format_hw_packet(&buffer[14], 3)); in mtk_hdmi_v2_hw_write_spd_infoframe()
190 regmap_write(hdmi->regs, TOP_SPDIF_PKT04, mtk_hdmi_v2_format_hw_packet(&buffer[17], 4)); in mtk_hdmi_v2_hw_write_spd_infoframe()
191 regmap_write(hdmi->regs, TOP_SPDIF_PKT05, mtk_hdmi_v2_format_hw_packet(&buffer[21], 3)); in mtk_hdmi_v2_hw_write_spd_infoframe()
192 regmap_write(hdmi->regs, TOP_SPDIF_PKT06, mtk_hdmi_v2_format_hw_packet(&buffer[24], 4)); in mtk_hdmi_v2_hw_write_spd_infoframe()
193 regmap_write(hdmi->regs, TOP_SPDIF_PKT07, buffer[28]); in mtk_hdmi_v2_hw_write_spd_infoframe()
195 regmap_set_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN); in mtk_hdmi_v2_hw_write_spd_infoframe()
196 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN); in mtk_hdmi_v2_hw_write_spd_infoframe()
199 static void mtk_hdmi_v2_hw_write_vendor_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer) in mtk_hdmi_v2_hw_write_vendor_infoframe() argument
201 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN); in mtk_hdmi_v2_hw_write_vendor_infoframe()
202 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN); in mtk_hdmi_v2_hw_write_vendor_infoframe()
204 regmap_write(hdmi->regs, TOP_VSIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3)); in mtk_hdmi_v2_hw_write_vendor_infoframe()
205 regmap_write(hdmi->regs, TOP_VSIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4)); in mtk_hdmi_v2_hw_write_vendor_infoframe()
206 regmap_write(hdmi->regs, TOP_VSIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 2)); in mtk_hdmi_v2_hw_write_vendor_infoframe()
207 regmap_write(hdmi->regs, TOP_VSIF_PKT02, 0); in mtk_hdmi_v2_hw_write_vendor_infoframe()
208 regmap_write(hdmi->regs, TOP_VSIF_PKT03, 0); in mtk_hdmi_v2_hw_write_vendor_infoframe()
209 regmap_write(hdmi->regs, TOP_VSIF_PKT04, 0); in mtk_hdmi_v2_hw_write_vendor_infoframe()
210 regmap_write(hdmi->regs, TOP_VSIF_PKT05, 0); in mtk_hdmi_v2_hw_write_vendor_infoframe()
211 regmap_write(hdmi->regs, TOP_VSIF_PKT06, 0); in mtk_hdmi_v2_hw_write_vendor_infoframe()
212 regmap_write(hdmi->regs, TOP_VSIF_PKT07, 0); in mtk_hdmi_v2_hw_write_vendor_infoframe()
214 regmap_set_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN); in mtk_hdmi_v2_hw_write_vendor_infoframe()
215 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN); in mtk_hdmi_v2_hw_write_vendor_infoframe()
218 static void mtk_hdmi_yuv420_downsampling(struct mtk_hdmi *hdmi, bool enable) in mtk_hdmi_yuv420_downsampling() argument
222 regmap_read(hdmi->regs, VID_DOWNSAMPLE_CONFIG, &val); in mtk_hdmi_yuv420_downsampling()
225 regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMI_YUV420_MODE); in mtk_hdmi_yuv420_downsampling()
230 regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val); in mtk_hdmi_yuv420_downsampling()
232 regmap_set_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE); in mtk_hdmi_yuv420_downsampling()
234 regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMI_YUV420_MODE); in mtk_hdmi_yuv420_downsampling()
239 regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val); in mtk_hdmi_yuv420_downsampling()
241 regmap_clear_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE); in mtk_hdmi_yuv420_downsampling()
245 static int mtk_hdmi_v2_setup_audio_infoframe(struct mtk_hdmi *hdmi) in mtk_hdmi_v2_setup_audio_infoframe() argument
247 struct hdmi_codec_params *params = &hdmi->aud_param.codec_params; in mtk_hdmi_v2_setup_audio_infoframe()
258 mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer); in mtk_hdmi_v2_setup_audio_infoframe()
263 static inline void mtk_hdmi_v2_hw_gcp_avmute(struct mtk_hdmi *hdmi, bool mute) in mtk_hdmi_v2_hw_gcp_avmute() argument
267 regmap_read(hdmi->regs, TOP_CFG01, &val); in mtk_hdmi_v2_hw_gcp_avmute()
277 regmap_write(hdmi->regs, TOP_CFG01, val); in mtk_hdmi_v2_hw_gcp_avmute()
279 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN); in mtk_hdmi_v2_hw_gcp_avmute()
280 regmap_set_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR); in mtk_hdmi_v2_hw_gcp_avmute()
283 static void mtk_hdmi_v2_hw_ncts_enable(struct mtk_hdmi *hdmi, bool enable) in mtk_hdmi_v2_hw_ncts_enable() argument
286 regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL); in mtk_hdmi_v2_hw_ncts_enable()
288 regmap_clear_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL); in mtk_hdmi_v2_hw_ncts_enable()
291 static void mtk_hdmi_v2_hw_aud_set_channel_status(struct mtk_hdmi *hdmi) in mtk_hdmi_v2_hw_aud_set_channel_status() argument
293 u8 *ch_status = hdmi->aud_param.codec_params.iec.status; in mtk_hdmi_v2_hw_aud_set_channel_status()
296 regmap_write(hdmi->regs, AIP_I2S_CHST0, mtk_hdmi_v2_format_hw_packet(&ch_status[0], 4)); in mtk_hdmi_v2_hw_aud_set_channel_status()
297 regmap_write(hdmi->regs, AIP_I2S_CHST1, mtk_hdmi_v2_format_hw_packet(&ch_status[4], 3)); in mtk_hdmi_v2_hw_aud_set_channel_status()
300 static void mtk_hdmi_v2_hw_aud_set_ncts(struct mtk_hdmi *hdmi, in mtk_hdmi_v2_hw_aud_set_ncts() argument
308 regmap_write(hdmi->regs, AIP_N_VAL, n); in mtk_hdmi_v2_hw_aud_set_ncts()
309 regmap_write(hdmi->regs, AIP_CTS_SVAL, cts); in mtk_hdmi_v2_hw_aud_set_ncts()
312 static void mtk_hdmi_v2_hw_aud_enable(struct mtk_hdmi *hdmi, bool enable) in mtk_hdmi_v2_hw_aud_enable() argument
315 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP); in mtk_hdmi_v2_hw_aud_enable()
317 regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP); in mtk_hdmi_v2_hw_aud_enable()
339 static void mtk_hdmi_audio_dsd_config(struct mtk_hdmi *hdmi, in mtk_hdmi_audio_dsd_config() argument
344 regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN | DSD_EN | HBRA_ON, DSD_EN); in mtk_hdmi_audio_dsd_config()
345 regmap_set_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN); in mtk_hdmi_audio_dsd_config()
352 regmap_write(hdmi->regs, TOP_AUD_MAP, channel_map); in mtk_hdmi_audio_dsd_config()
353 regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN); in mtk_hdmi_audio_dsd_config()
356 static inline void mtk_hdmi_v2_hw_i2s_fifo_map(struct mtk_hdmi *hdmi, u32 fifo_mapping) in mtk_hdmi_v2_hw_i2s_fifo_map() argument
358 regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, in mtk_hdmi_v2_hw_i2s_fifo_map()
362 static inline void mtk_hdmi_v2_hw_i2s_ch_number(struct mtk_hdmi *hdmi, u8 chnum) in mtk_hdmi_v2_hw_i2s_ch_number() argument
364 regmap_update_bits(hdmi->regs, AIP_CTRL, I2S_EN, FIELD_PREP(I2S_EN, chnum)); in mtk_hdmi_v2_hw_i2s_ch_number()
367 static void mtk_hdmi_v2_hw_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 chnum, u8 mapping) in mtk_hdmi_v2_hw_i2s_ch_mapping() argument
398 mtk_hdmi_v2_hw_i2s_fifo_map(hdmi, fifo_map); in mtk_hdmi_v2_hw_i2s_ch_mapping()
399 mtk_hdmi_v2_hw_i2s_ch_number(hdmi, bdata); in mtk_hdmi_v2_hw_i2s_ch_mapping()
402 * Set HDMI Audio packet layout indicator: in mtk_hdmi_v2_hw_i2s_ch_mapping()
407 regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1); in mtk_hdmi_v2_hw_i2s_ch_mapping()
409 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1); in mtk_hdmi_v2_hw_i2s_ch_mapping()
412 static void mtk_hdmi_i2s_data_fmt(struct mtk_hdmi *hdmi, unsigned char fmt) in mtk_hdmi_i2s_data_fmt() argument
416 regmap_read(hdmi->regs, AIP_I2S_CTRL, &val); in mtk_hdmi_i2s_data_fmt()
434 regmap_write(hdmi->regs, AIP_I2S_CTRL, val); in mtk_hdmi_i2s_data_fmt()
437 static inline void mtk_hdmi_i2s_sck_edge_rise(struct mtk_hdmi *hdmi, bool rise) in mtk_hdmi_i2s_sck_edge_rise() argument
440 regmap_set_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE); in mtk_hdmi_i2s_sck_edge_rise()
442 regmap_clear_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE); in mtk_hdmi_i2s_sck_edge_rise()
445 static inline void mtk_hdmi_i2s_cbit_order(struct mtk_hdmi *hdmi, unsigned int cbit) in mtk_hdmi_i2s_cbit_order() argument
447 regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, CBIT_ORDER_SAME, cbit); in mtk_hdmi_i2s_cbit_order()
450 static inline void mtk_hdmi_i2s_vbit(struct mtk_hdmi *hdmi, unsigned int vbit) in mtk_hdmi_i2s_vbit() argument
453 regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, VBIT_COMPRESSED, vbit); in mtk_hdmi_i2s_vbit()
456 static inline void mtk_hdmi_i2s_data_direction(struct mtk_hdmi *hdmi, unsigned int is_lsb) in mtk_hdmi_i2s_data_direction() argument
458 regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, I2S_DATA_DIR_LSB, is_lsb); in mtk_hdmi_i2s_data_direction()
461 static inline void mtk_hdmi_v2_hw_audio_type(struct mtk_hdmi *hdmi, unsigned int spdif_i2s) in mtk_hdmi_v2_hw_audio_type() argument
463 regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN, FIELD_PREP(SPDIF_EN, spdif_i2s)); in mtk_hdmi_v2_hw_audio_type()
466 static u8 mtk_hdmi_v2_get_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 channel_type) in mtk_hdmi_v2_get_i2s_ch_mapping() argument
537 static inline void mtk_hdmi_v2_hw_i2s_ch_swap(struct mtk_hdmi *hdmi) in mtk_hdmi_v2_hw_i2s_ch_swap() argument
539 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE, in mtk_hdmi_v2_hw_i2s_ch_swap()
543 static void mtk_hdmi_hbr_config(struct mtk_hdmi *hdmi, bool dsd_bypass) in mtk_hdmi_hbr_config() argument
548 regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, HBRA_ON); in mtk_hdmi_hbr_config()
549 regmap_set_bits(hdmi->regs, AIP_CTRL, I2S_EN); in mtk_hdmi_hbr_config()
551 regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, SPDIF_EN); in mtk_hdmi_hbr_config()
552 regmap_set_bits(hdmi->regs, AIP_CTRL, SPDIF_INTERNAL_MODULE); in mtk_hdmi_hbr_config()
553 regmap_set_bits(hdmi->regs, AIP_CTRL, HBR_FROM_SPDIF); in mtk_hdmi_hbr_config()
554 regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_CAL_N4); in mtk_hdmi_hbr_config()
558 static inline void mtk_hdmi_v2_hw_spdif_config(struct mtk_hdmi *hdmi) in mtk_hdmi_v2_hw_spdif_config() argument
560 regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_1UI_LOCK); in mtk_hdmi_v2_hw_spdif_config()
561 regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, FS_OVERRIDE_WRITE); in mtk_hdmi_v2_hw_spdif_config()
562 regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_2UI_LOCK); in mtk_hdmi_v2_hw_spdif_config()
564 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_1UI_WRITE, in mtk_hdmi_v2_hw_spdif_config()
566 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_SPDIF_WRITE, in mtk_hdmi_v2_hw_spdif_config()
568 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, AUD_ERR_THRESH, in mtk_hdmi_v2_hw_spdif_config()
571 regmap_set_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN); in mtk_hdmi_v2_hw_spdif_config()
574 static void mtk_hdmi_v2_aud_set_input(struct mtk_hdmi *hdmi) in mtk_hdmi_v2_aud_set_input() argument
576 struct hdmi_audio_param *aud_param = &hdmi->aud_param; in mtk_hdmi_v2_aud_set_input()
583 regmap_write(hdmi->regs, TOP_AUD_MAP, out_ch_map); in mtk_hdmi_v2_aud_set_input()
585 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE, 0); in mtk_hdmi_v2_aud_set_input()
586 regmap_clear_bits(hdmi->regs, AIP_CTRL, in mtk_hdmi_v2_aud_set_input()
589 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN | AUD_LAYOUT_1); in mtk_hdmi_v2_aud_set_input()
595 mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt); in mtk_hdmi_v2_aud_set_input()
596 mtk_hdmi_hbr_config(hdmi, true); in mtk_hdmi_v2_aud_set_input()
599 mtk_hdmi_audio_dsd_config(hdmi, codec_params->channels, 0); in mtk_hdmi_v2_aud_set_input()
600 mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, codec_params->channels, 1); in mtk_hdmi_v2_aud_set_input()
603 mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt); in mtk_hdmi_v2_aud_set_input()
604 mtk_hdmi_i2s_sck_edge_rise(hdmi, true); in mtk_hdmi_v2_aud_set_input()
605 mtk_hdmi_i2s_cbit_order(hdmi, CBIT_ORDER_SAME); in mtk_hdmi_v2_aud_set_input()
606 mtk_hdmi_i2s_vbit(hdmi, 0); /* PCM data */ in mtk_hdmi_v2_aud_set_input()
607 mtk_hdmi_i2s_data_direction(hdmi, 0); /* MSB first */ in mtk_hdmi_v2_aud_set_input()
608 mtk_hdmi_v2_hw_audio_type(hdmi, HDMI_AUD_INPUT_I2S); in mtk_hdmi_v2_aud_set_input()
609 i2s_ch_map = mtk_hdmi_v2_get_i2s_ch_mapping(hdmi, in mtk_hdmi_v2_aud_set_input()
611 mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, codec_params->channels, i2s_ch_map); in mtk_hdmi_v2_aud_set_input()
612 mtk_hdmi_v2_hw_i2s_ch_swap(hdmi); in mtk_hdmi_v2_aud_set_input()
618 mtk_hdmi_hbr_config(hdmi, false); in mtk_hdmi_v2_aud_set_input()
620 mtk_hdmi_v2_hw_spdif_config(hdmi); in mtk_hdmi_v2_aud_set_input()
621 mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, 2, 0); in mtk_hdmi_v2_aud_set_input()
626 static inline void mtk_hdmi_v2_hw_audio_input_enable(struct mtk_hdmi *hdmi, bool ena) in mtk_hdmi_v2_hw_audio_input_enable() argument
629 regmap_set_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN); in mtk_hdmi_v2_hw_audio_input_enable()
631 regmap_clear_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN); in mtk_hdmi_v2_hw_audio_input_enable()
634 static void mtk_hdmi_v2_aip_ctrl_init(struct mtk_hdmi *hdmi) in mtk_hdmi_v2_aip_ctrl_init() argument
636 regmap_set_bits(hdmi->regs, AIP_CTRL, in mtk_hdmi_v2_aip_ctrl_init()
638 regmap_clear_bits(hdmi->regs, AIP_TPI_CTRL, TPI_AUDIO_LOOKUP_EN); in mtk_hdmi_v2_aip_ctrl_init()
641 static void mtk_hdmi_v2_audio_reset(struct mtk_hdmi *hdmi, bool reset) in mtk_hdmi_v2_audio_reset() argument
646 regmap_set_bits(hdmi->regs, AIP_TXCTRL, arst_bits); in mtk_hdmi_v2_audio_reset()
648 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, arst_bits); in mtk_hdmi_v2_audio_reset()
651 static void mtk_hdmi_v2_aud_output_config(struct mtk_hdmi *hdmi, in mtk_hdmi_v2_aud_output_config() argument
654 /* Shut down and reset the HDMI Audio HW to avoid glitching */ in mtk_hdmi_v2_aud_output_config()
655 mtk_hdmi_v2_hw_aud_mute(hdmi, true); in mtk_hdmi_v2_aud_output_config()
656 mtk_hdmi_v2_hw_aud_enable(hdmi, false); in mtk_hdmi_v2_aud_output_config()
657 mtk_hdmi_v2_audio_reset(hdmi, true); in mtk_hdmi_v2_aud_output_config()
660 mtk_hdmi_v2_aip_ctrl_init(hdmi); in mtk_hdmi_v2_aud_output_config()
661 mtk_hdmi_v2_aud_set_input(hdmi); in mtk_hdmi_v2_aud_output_config()
662 mtk_hdmi_v2_hw_aud_set_channel_status(hdmi); in mtk_hdmi_v2_aud_output_config()
663 mtk_hdmi_v2_setup_audio_infoframe(hdmi); in mtk_hdmi_v2_aud_output_config()
664 mtk_hdmi_v2_hw_audio_input_enable(hdmi, true); in mtk_hdmi_v2_aud_output_config()
665 mtk_hdmi_v2_audio_reset(hdmi, false); in mtk_hdmi_v2_aud_output_config()
668 mtk_hdmi_v2_hw_ncts_enable(hdmi, false); in mtk_hdmi_v2_aud_output_config()
669 mtk_hdmi_v2_hw_aud_set_ncts(hdmi, hdmi->aud_param.codec_params.sample_rate, in mtk_hdmi_v2_aud_output_config()
676 mtk_hdmi_v2_hw_ncts_enable(hdmi, true); in mtk_hdmi_v2_aud_output_config()
677 mtk_hdmi_v2_hw_aud_enable(hdmi, true); in mtk_hdmi_v2_aud_output_config()
678 mtk_hdmi_v2_hw_aud_mute(hdmi, false); in mtk_hdmi_v2_aud_output_config()
681 static void mtk_hdmi_v2_change_video_resolution(struct mtk_hdmi *hdmi, in mtk_hdmi_v2_change_video_resolution() argument
684 mtk_hdmi_v2_hw_reset(hdmi); in mtk_hdmi_v2_change_video_resolution()
685 mtk_hdmi_v2_set_sw_hpd(hdmi, true); in mtk_hdmi_v2_change_video_resolution()
688 regmap_write(hdmi->regs, HDCP_TOP_CTRL, 0); in mtk_hdmi_v2_change_video_resolution()
694 regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HDCP2X_RX_REAUTH_REQ_DDCM_INT); in mtk_hdmi_v2_change_video_resolution()
697 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true); in mtk_hdmi_v2_change_video_resolution()
700 regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR); in mtk_hdmi_v2_change_video_resolution()
701 regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW); in mtk_hdmi_v2_change_video_resolution()
704 regmap_update_bits(hdmi->regs, TOP_CFG00, TMDS_PACK_MODE, in mtk_hdmi_v2_change_video_resolution()
707 regmap_clear_bits(hdmi->regs, TOP_CFG00, DEEPCOLOR_PKT_EN); in mtk_hdmi_v2_change_video_resolution()
709 regmap_clear_bits(hdmi->regs, TOP_MISC_CTLR, DEEP_COLOR_ADD); in mtk_hdmi_v2_change_video_resolution()
711 if (hdmi->curr_conn->display_info.is_hdmi) in mtk_hdmi_v2_change_video_resolution()
712 regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI); in mtk_hdmi_v2_change_video_resolution()
714 regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI); in mtk_hdmi_v2_change_video_resolution()
717 mtk_hdmi_v2_hw_vid_mute(hdmi, true); in mtk_hdmi_v2_change_video_resolution()
718 mtk_hdmi_v2_hw_aud_mute(hdmi, true); in mtk_hdmi_v2_change_video_resolution()
719 mtk_hdmi_v2_hw_gcp_avmute(hdmi, false); in mtk_hdmi_v2_change_video_resolution()
721 regmap_update_bits(hdmi->regs, TOP_CFG01, in mtk_hdmi_v2_change_video_resolution()
726 mtk_hdmi_v2_enable_scrambling(hdmi, hdmi->mode.clock >= 340 * KILO); in mtk_hdmi_v2_change_video_resolution()
728 switch (conn_state->hdmi.output_format) { in mtk_hdmi_v2_change_video_resolution()
733 mtk_hdmi_yuv420_downsampling(hdmi, false); in mtk_hdmi_v2_change_video_resolution()
742 mtk_hdmi_yuv420_downsampling(hdmi, false); in mtk_hdmi_v2_change_video_resolution()
743 regmap_set_bits(hdmi->regs, VID_DOWNSAMPLE_CONFIG, in mtk_hdmi_v2_change_video_resolution()
747 mtk_hdmi_yuv420_downsampling(hdmi, true); in mtk_hdmi_v2_change_video_resolution()
752 static void mtk_hdmi_v2_output_set_display_mode(struct mtk_hdmi *hdmi, in mtk_hdmi_v2_output_set_display_mode() argument
757 .dp = { .link_rate = hdmi->mode.clock * KILO } in mtk_hdmi_v2_output_set_display_mode()
761 ret = phy_configure(hdmi->phy, &opts); in mtk_hdmi_v2_output_set_display_mode()
763 dev_err(hdmi->dev, "Setting clock=%d failed: %d", mode->clock, ret); in mtk_hdmi_v2_output_set_display_mode()
765 mtk_hdmi_v2_change_video_resolution(hdmi, conn_state); in mtk_hdmi_v2_output_set_display_mode()
766 mtk_hdmi_v2_aud_output_config(hdmi, mode); in mtk_hdmi_v2_output_set_display_mode()
769 static int mtk_hdmi_v2_clk_enable(struct mtk_hdmi *hdmi) in mtk_hdmi_v2_clk_enable() argument
773 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]); in mtk_hdmi_v2_clk_enable()
777 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]); in mtk_hdmi_v2_clk_enable()
781 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]); in mtk_hdmi_v2_clk_enable()
785 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]); in mtk_hdmi_v2_clk_enable()
792 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]); in mtk_hdmi_v2_clk_enable()
794 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]); in mtk_hdmi_v2_clk_enable()
796 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]); in mtk_hdmi_v2_clk_enable()
801 static void mtk_hdmi_v2_clk_disable(struct mtk_hdmi *hdmi) in mtk_hdmi_v2_clk_disable() argument
803 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]); in mtk_hdmi_v2_clk_disable()
804 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]); in mtk_hdmi_v2_clk_disable()
805 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]); in mtk_hdmi_v2_clk_disable()
806 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]); in mtk_hdmi_v2_clk_disable()
809 static enum hdmi_hpd_state mtk_hdmi_v2_hpd_pord_status(struct mtk_hdmi *hdmi) in mtk_hdmi_v2_hpd_pord_status() argument
814 regmap_read(hdmi->regs, HPD_DDC_STATUS, &hpd_status); in mtk_hdmi_v2_hpd_pord_status()
821 * the HDMI spec for reading EDID and for HDMI Audio registers to in mtk_hdmi_v2_hpd_pord_status()
843 struct mtk_hdmi *hdmi = arg; in mtk_hdmi_v2_isr() local
847 regmap_read(hdmi->regs, TOP_INT_STA00, &irq_sta); in mtk_hdmi_v2_isr()
855 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, false); in mtk_hdmi_v2_isr()
859 regmap_write(hdmi->regs, TOP_INT_CLR00, HPD_PORD_HWIRQS); in mtk_hdmi_v2_isr()
860 regmap_write(hdmi->regs, TOP_INT_CLR00, 0); in mtk_hdmi_v2_isr()
866 static irqreturn_t __mtk_hdmi_v2_isr_thread(struct mtk_hdmi *hdmi) in __mtk_hdmi_v2_isr_thread() argument
870 hpd = mtk_hdmi_v2_hpd_pord_status(hdmi); in __mtk_hdmi_v2_isr_thread()
871 if (hpd != hdmi->hpd) { in __mtk_hdmi_v2_isr_thread()
872 struct drm_encoder *encoder = hdmi->bridge.encoder; in __mtk_hdmi_v2_isr_thread()
874 hdmi->hpd = hpd; in __mtk_hdmi_v2_isr_thread()
877 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev); in __mtk_hdmi_v2_isr_thread()
880 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true); in __mtk_hdmi_v2_isr_thread()
886 struct mtk_hdmi *hdmi = arg; in mtk_hdmi_v2_isr_thread() local
889 * Debounce HDMI monitor HPD status. in mtk_hdmi_v2_isr_thread()
894 return __mtk_hdmi_v2_isr_thread(hdmi); in mtk_hdmi_v2_isr_thread()
897 static int mtk_hdmi_v2_enable(struct mtk_hdmi *hdmi) in mtk_hdmi_v2_enable() argument
899 bool was_active = pm_runtime_active(hdmi->dev); in mtk_hdmi_v2_enable()
902 ret = pm_runtime_resume_and_get(hdmi->dev); in mtk_hdmi_v2_enable()
904 dev_err(hdmi->dev, "Cannot resume HDMI\n"); in mtk_hdmi_v2_enable()
908 ret = mtk_hdmi_v2_clk_enable(hdmi); in mtk_hdmi_v2_enable()
910 pm_runtime_put(hdmi->dev); in mtk_hdmi_v2_enable()
915 mtk_hdmi_v2_hw_reset(hdmi); in mtk_hdmi_v2_enable()
916 mtk_hdmi_v2_set_sw_hpd(hdmi, true); in mtk_hdmi_v2_enable()
922 static void mtk_hdmi_v2_disable(struct mtk_hdmi *hdmi) in mtk_hdmi_v2_disable() argument
924 mtk_hdmi_v2_clk_disable(hdmi); in mtk_hdmi_v2_disable()
925 pm_runtime_put_sync(hdmi->dev); in mtk_hdmi_v2_disable()
936 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_attach() local
943 if (hdmi->next_bridge) { in mtk_hdmi_v2_bridge_attach()
944 ret = drm_bridge_attach(encoder, hdmi->next_bridge, bridge, flags); in mtk_hdmi_v2_bridge_attach()
949 ret = mtk_hdmi_v2_enable(hdmi); in mtk_hdmi_v2_bridge_attach()
954 regmap_set_bits(hdmi->regs, HPD_DDC_CTRL, in mtk_hdmi_v2_bridge_attach()
957 irq_clear_status_flags(hdmi->irq, IRQ_NOAUTOEN); in mtk_hdmi_v2_bridge_attach()
958 enable_irq(hdmi->irq); in mtk_hdmi_v2_bridge_attach()
961 * Check if any HDMI monitor was connected before probing this driver in mtk_hdmi_v2_bridge_attach()
967 __mtk_hdmi_v2_isr_thread(hdmi); in mtk_hdmi_v2_bridge_attach()
969 mtk_hdmi_v2_disable(hdmi); in mtk_hdmi_v2_bridge_attach()
976 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_detach() local
978 WARN_ON(pm_runtime_active(hdmi->dev)); in mtk_hdmi_v2_bridge_detach()
981 disable_irq(hdmi->irq); in mtk_hdmi_v2_bridge_detach()
984 static void mtk_hdmi_v2_handle_plugged_change(struct mtk_hdmi *hdmi, bool plugged) in mtk_hdmi_v2_handle_plugged_change() argument
986 mutex_lock(&hdmi->update_plugged_status_lock); in mtk_hdmi_v2_handle_plugged_change()
987 if (hdmi->plugged_cb && hdmi->codec_dev) in mtk_hdmi_v2_handle_plugged_change()
988 hdmi->plugged_cb(hdmi->codec_dev, plugged); in mtk_hdmi_v2_handle_plugged_change()
989 mutex_unlock(&hdmi->update_plugged_status_lock); in mtk_hdmi_v2_handle_plugged_change()
995 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_pre_enable() local
998 .dp = { .link_rate = hdmi->mode.clock * KILO } in mtk_hdmi_v2_bridge_pre_enable()
1003 ret = mtk_hdmi_v2_enable(hdmi); in mtk_hdmi_v2_bridge_pre_enable()
1008 hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); in mtk_hdmi_v2_bridge_pre_enable()
1010 conn_state = drm_atomic_get_new_connector_state(state, hdmi->curr_conn); in mtk_hdmi_v2_bridge_pre_enable()
1015 * Preconfigure the HDMI controller and the HDMI PHY at pre_enable in mtk_hdmi_v2_bridge_pre_enable()
1019 mtk_hdmi_v2_output_set_display_mode(hdmi, conn_state, &hdmi->mode); in mtk_hdmi_v2_bridge_pre_enable()
1022 phy_configure(hdmi->phy, &opts); in mtk_hdmi_v2_bridge_pre_enable()
1025 phy_power_on(hdmi->phy); in mtk_hdmi_v2_bridge_pre_enable()
1027 hdmi->powered = true; in mtk_hdmi_v2_bridge_pre_enable()
1033 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_enable() local
1036 if (WARN_ON(!hdmi->powered)) in mtk_hdmi_v2_bridge_enable()
1039 ret = drm_atomic_helper_connector_hdmi_update_infoframes(hdmi->curr_conn, state); in mtk_hdmi_v2_bridge_enable()
1041 dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret); in mtk_hdmi_v2_bridge_enable()
1043 mtk_hdmi_v2_hw_vid_mute(hdmi, false); in mtk_hdmi_v2_bridge_enable()
1046 mtk_hdmi_v2_handle_plugged_change(hdmi, true); in mtk_hdmi_v2_bridge_enable()
1048 hdmi->enabled = true; in mtk_hdmi_v2_bridge_enable()
1054 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_disable() local
1056 if (!hdmi->enabled) in mtk_hdmi_v2_bridge_disable()
1059 mtk_hdmi_v2_hw_gcp_avmute(hdmi, true); in mtk_hdmi_v2_bridge_disable()
1061 mtk_hdmi_v2_hw_vid_mute(hdmi, true); in mtk_hdmi_v2_bridge_disable()
1062 mtk_hdmi_v2_hw_aud_mute(hdmi, true); in mtk_hdmi_v2_bridge_disable()
1065 hdmi->enabled = false; in mtk_hdmi_v2_bridge_disable()
1071 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_post_disable() local
1073 if (!hdmi->powered) in mtk_hdmi_v2_bridge_post_disable()
1076 phy_power_off(hdmi->phy); in mtk_hdmi_v2_bridge_post_disable()
1077 hdmi->powered = false; in mtk_hdmi_v2_bridge_post_disable()
1080 mtk_hdmi_v2_handle_plugged_change(hdmi, false); in mtk_hdmi_v2_bridge_post_disable()
1083 mtk_hdmi_v2_disable(hdmi); in mtk_hdmi_v2_bridge_post_disable()
1089 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_detect() local
1091 return hdmi->hpd != HDMI_PLUG_OUT ? in mtk_hdmi_v2_bridge_detect()
1103 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_hpd_enable() local
1106 ret = mtk_hdmi_v2_enable(hdmi); in mtk_hdmi_v2_hpd_enable()
1108 dev_err(hdmi->dev, "Cannot power on controller for HPD: %d\n", ret); in mtk_hdmi_v2_hpd_enable()
1112 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, true); in mtk_hdmi_v2_hpd_enable()
1117 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_hpd_disable() local
1119 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, false); in mtk_hdmi_v2_hpd_disable()
1120 mtk_hdmi_v2_disable(hdmi); in mtk_hdmi_v2_hpd_disable()
1138 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_hdmi_clear_infoframe() local
1142 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN_WR | AUD_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1143 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1146 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1147 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1150 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1151 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1154 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1155 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1169 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_hdmi_write_infoframe() local
1173 mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer); in mtk_hdmi_v2_hdmi_write_infoframe()
1176 mtk_hdmi_v2_hw_write_avi_infoframe(hdmi, buffer); in mtk_hdmi_v2_hdmi_write_infoframe()
1179 mtk_hdmi_v2_hw_write_spd_infoframe(hdmi, buffer); in mtk_hdmi_v2_hdmi_write_infoframe()
1182 mtk_hdmi_v2_hw_write_vendor_infoframe(hdmi, buffer); in mtk_hdmi_v2_hdmi_write_infoframe()
1186 dev_err(hdmi->dev, "Unsupported HDMI infoframe type %u\n", type); in mtk_hdmi_v2_hdmi_write_infoframe()
1193 static int mtk_hdmi_v2_set_abist(struct mtk_hdmi *hdmi, bool enable) in mtk_hdmi_v2_set_abist() argument
1195 struct drm_display_mode *mode = &hdmi->mode; in mtk_hdmi_v2_set_abist()
1200 regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE); in mtk_hdmi_v2_set_abist()
1244 regmap_update_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_VIDEO_FORMAT, in mtk_hdmi_v2_set_abist()
1246 regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE); in mtk_hdmi_v2_set_abist()
1252 struct mtk_hdmi *hdmi = m->private; in mtk_hdmi_v2_debug_abist_show() local
1257 if (!hdmi) in mtk_hdmi_v2_debug_abist_show()
1260 ret = regmap_read(hdmi->regs, TOP_CFG00, &val); in mtk_hdmi_v2_debug_abist_show()
1266 seq_printf(m, "HDMI Automated Built-In Self Test: %s\n", in mtk_hdmi_v2_debug_abist_show()
1338 * HDMI audio codec callbacks
1344 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); in mtk_hdmi_v2_audio_hook_plugged_cb() local
1347 if (!hdmi) in mtk_hdmi_v2_audio_hook_plugged_cb()
1350 mtk_hdmi_audio_set_plugged_cb(hdmi, fn, codec_dev); in mtk_hdmi_v2_audio_hook_plugged_cb()
1351 plugged = (hdmi->hpd == HDMI_PLUG_IN_AND_SINK_POWER_ON); in mtk_hdmi_v2_audio_hook_plugged_cb()
1352 mtk_hdmi_v2_handle_plugged_change(hdmi, plugged); in mtk_hdmi_v2_audio_hook_plugged_cb()
1361 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); in mtk_hdmi_v2_audio_hw_params() local
1363 if (hdmi->audio_enable) { in mtk_hdmi_v2_audio_hw_params()
1364 mtk_hdmi_audio_params(hdmi, daifmt, params); in mtk_hdmi_v2_audio_hw_params()
1365 mtk_hdmi_v2_aud_output_config(hdmi, &hdmi->mode); in mtk_hdmi_v2_audio_hw_params()
1372 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); in mtk_hdmi_v2_audio_startup() local
1374 mtk_hdmi_v2_hw_aud_enable(hdmi, true); in mtk_hdmi_v2_audio_startup()
1375 hdmi->audio_enable = true; in mtk_hdmi_v2_audio_startup()
1382 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); in mtk_hdmi_v2_audio_shutdown() local
1384 hdmi->audio_enable = false; in mtk_hdmi_v2_audio_shutdown()
1385 mtk_hdmi_v2_hw_aud_enable(hdmi, false); in mtk_hdmi_v2_audio_shutdown()
1390 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); in mtk_hdmi_v2_audio_mute() local
1392 mtk_hdmi_v2_hw_aud_mute(hdmi, enable); in mtk_hdmi_v2_audio_mute()
1408 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); in mtk_hdmi_v2_suspend() local
1410 mtk_hdmi_v2_disable(hdmi); in mtk_hdmi_v2_suspend()
1417 struct mtk_hdmi *hdmi = dev_get_drvdata(dev); in mtk_hdmi_v2_resume() local
1419 return mtk_hdmi_v2_enable(hdmi); in mtk_hdmi_v2_resume()
1444 struct mtk_hdmi *hdmi; in mtk_hdmi_v2_probe() local
1447 /* Populate HDMI sub-devices if present */ in mtk_hdmi_v2_probe()
1452 hdmi = mtk_hdmi_common_probe(pdev); in mtk_hdmi_v2_probe()
1453 if (IS_ERR(hdmi)) in mtk_hdmi_v2_probe()
1454 return PTR_ERR(hdmi); in mtk_hdmi_v2_probe()
1456 hdmi->hpd = HDMI_PLUG_OUT; in mtk_hdmi_v2_probe()
1459 mtk_hdmi_v2_hwirq_disable(hdmi); in mtk_hdmi_v2_probe()
1462 * In case bootloader leaves HDMI enabled before booting, make in mtk_hdmi_v2_probe()
1466 regmap_write(hdmi->regs, TOP_INT_CLR00, GENMASK(31, 0)); in mtk_hdmi_v2_probe()
1467 regmap_write(hdmi->regs, TOP_INT_CLR01, GENMASK(18, 0)); in mtk_hdmi_v2_probe()
1470 regmap_write(hdmi->regs, TOP_INT_CLR00, 0); in mtk_hdmi_v2_probe()
1471 regmap_write(hdmi->regs, TOP_INT_CLR01, 0); in mtk_hdmi_v2_probe()
1478 irq_set_status_flags(hdmi->irq, IRQ_NOAUTOEN); in mtk_hdmi_v2_probe()
1479 ret = devm_request_threaded_irq(&pdev->dev, hdmi->irq, mtk_hdmi_v2_isr, in mtk_hdmi_v2_probe()
1482 dev_name(&pdev->dev), hdmi); in mtk_hdmi_v2_probe()
1495 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev); in mtk_hdmi_v2_remove() local
1497 i2c_put_adapter(hdmi->ddc_adpt); in mtk_hdmi_v2_remove()
1501 { .compatible = "mediatek,mt8188-hdmi-tx", .data = &mtk_hdmi_conf_mt8188 },
1502 { .compatible = "mediatek,mt8195-hdmi-tx", .data = &mtk_hdmi_conf_mt8195 },
1511 .name = "mediatek-drm-hdmi-v2",