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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmvebu-gated-clock.txt7 corresponding clock gating control bit in HW to ease manual clock
177 "marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
178 "marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
179 "marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
180 "marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
181 "marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
182 "marvell,mv98dx3236-gating-clock" - for 98dx3236 SoC clock gating
183 "marvell,dove-gating-clock" - for Dove SoC clock gating
184 "marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
185 - reg : shall be the register address of the Clock Gating Control register
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H A Dzx296718-clk.txt10 zx296718 top clock selection, divider and gating
14 zx296718 device level clock selection and gating
17 zx296718 audio clock selection, divider and gating
H A Dzx296702-clk.txt10 zx296702 top clock selection, divider and gating
14 zx296702 device level clock selection and gating
H A Dimx8qxp-lpcg.yaml7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
17 This level of clock gating is provided after the clocks are generated
H A Dimx7ulp-clock.txt25 clock gating mode.
39 optional division and clock gating mode for peripherals in their
H A Dti-keystone-pllctrl.txt6 divisions, gating, and synchronization.
H A Dbrcm,bcm2835-aux-clock.txt7 area controlling clock gating to the peripherals, and providing an IRQ
H A Dimx8ulp-pcc-clock.yaml15 software reset, clock selection, optional division and clock gating mode
H A Dlpc1850-creg-clk.txt5 32 kHz oscillator driver with power up/down and clock gating. Next
H A Dnvidia,tegra210-car.txt7 for muxing and gating Tegra's clocks, and setting their rates.
H A Daltr_socfpga.txt22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
H A Dnvidia,tegra30-car.txt7 for muxing and gating Tegra's clocks, and setting their rates.
H A Dnvidia,tegra114-car.txt7 for muxing and gating Tegra's clocks, and setting their rates.
H A Dnvidia,tegra20-car.txt7 for muxing and gating Tegra's clocks, and setting their rates.
H A Dimx8mp-audiomix.yaml13 NXP i.MX8M Plus AudioMIX is dedicated clock muxing and gating IP
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml79 Defines the memory self-refresh and controller clock gating idle period.
81 arg gating started if bus is idle for sr_mc_gate_idle*1024 DFI clock
300 Defines the memory self-refresh and controller clock gating idle period in nanoseconds.
302 arg gating started if bus is idle for sr_mc_gate_idle nanoseconds.
330 Defines the self-refresh and memory-controller clock gating disable
/freebsd/sys/contrib/device-tree/Bindings/power/
H A Dfsl,imx-gpc.yaml14 counters and Power Gating Control (PGC).
18 described as subnodes of the power gating controller 'pgc' node of the GPC.
H A Dfsl,imx-gpcv2.yaml13 The i.MX7S/D General Power Control (GPC) block contains Power Gating
19 described as subnodes of the power gating controller 'pgc' node.
/freebsd/sys/contrib/device-tree/Bindings/arm/msm/
H A Dqcom,idle-state.txt13 Standby: Standby does a little more in addition to architectural clock gating.
15 clocks. In addition to gating the clocks, QCOM cpus use this instruction as a
/freebsd/sys/dev/bhnd/cores/chipc/pwrctl/
H A Dbhnd_pwrctl_hostb_if.m100 * @param child The bhnd device requesting clock gating.
117 * @param child The bhnd device requesting clock gating.
/freebsd/sys/contrib/device-tree/Bindings/arm/marvell/
H A Dkirkwood.txt13 where the "powersave" clock is a gating clock used to switch the CPU
/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dl2c2x0.yaml198 arm,dynamic-clock-gating:
200 L2 dynamic clock gating. Value: <0> (forcibly
/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Drk3399_dmc.txt47 clock gating idle period. Memories are placed
49 clock arg gating started if bus is idle for
/freebsd/sys/contrib/device-tree/Bindings/cache/
H A Dl2c2x0.yaml198 arm,dynamic-clock-gating:
200 L2 dynamic clock gating. Value: <0> (forcibly
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5311reg.h25 #define AR5311_QDCLKGATE 0x005c /* MAC QCU/DCU clock gating control */

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