1*c66ec88fSEmmanuel VadotDevice Tree Clock bindings for ZTE zx296702 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotThis binding uses the common clock binding[1]. 4*c66ec88fSEmmanuel Vadot 5*c66ec88fSEmmanuel Vadot[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel VadotRequired properties: 8*c66ec88fSEmmanuel Vadot- compatible : shall be one of the following: 9*c66ec88fSEmmanuel Vadot "zte,zx296702-topcrm-clk": 10*c66ec88fSEmmanuel Vadot zx296702 top clock selection, divider and gating 11*c66ec88fSEmmanuel Vadot 12*c66ec88fSEmmanuel Vadot "zte,zx296702-lsp0crpm-clk" and 13*c66ec88fSEmmanuel Vadot "zte,zx296702-lsp1crpm-clk": 14*c66ec88fSEmmanuel Vadot zx296702 device level clock selection and gating 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel Vadot- reg: Address and length of the register set 17*c66ec88fSEmmanuel Vadot 18*c66ec88fSEmmanuel VadotThe clock consumer should specify the desired clock by having the clock 19*c66ec88fSEmmanuel VadotID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h 20*c66ec88fSEmmanuel Vadotfor the full list of zx296702 clock IDs. 21*c66ec88fSEmmanuel Vadot 22*c66ec88fSEmmanuel Vadot 23*c66ec88fSEmmanuel Vadottopclk: topcrm@09800000 { 24*c66ec88fSEmmanuel Vadot compatible = "zte,zx296702-topcrm-clk"; 25*c66ec88fSEmmanuel Vadot reg = <0x09800000 0x1000>; 26*c66ec88fSEmmanuel Vadot #clock-cells = <1>; 27*c66ec88fSEmmanuel Vadot}; 28*c66ec88fSEmmanuel Vadot 29*c66ec88fSEmmanuel Vadotuart0: serial@09405000 { 30*c66ec88fSEmmanuel Vadot compatible = "zte,zx296702-uart"; 31*c66ec88fSEmmanuel Vadot reg = <0x09405000 0x1000>; 32*c66ec88fSEmmanuel Vadot interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 33*c66ec88fSEmmanuel Vadot clocks = <&lsp1clk ZX296702_UART0_PCLK>; 34*c66ec88fSEmmanuel Vadot}; 35