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/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c34 { .name = "etnaviv-gpu,2d" },
42 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
44 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
48 *value = gpu->identity.model; in etnaviv_gpu_get_param()
52 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
56 *value = gpu->identity.features; in etnaviv_gpu_get_param()
60 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
64 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
68 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
72 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
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H A Detnaviv_drv.c51 struct etnaviv_gpu *g = priv->gpu[i]; in load_gpu()
58 priv->gpu[i] = NULL; in load_gpu()
86 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_open() local
89 if (gpu) { in etnaviv_open()
90 sched = &gpu->sched; in etnaviv_open()
113 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_postclose() local
115 if (gpu) in etnaviv_postclose()
151 static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m) in etnaviv_mmu_show() argument
156 seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev)); in etnaviv_mmu_show()
159 * Lock the GPU to avoid a MMU context switch just now and elevate in etnaviv_mmu_show()
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H A Detnaviv_iommu_v2.c165 static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_nonsec() argument
172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
175 if (gpu->mmu_context) in etnaviv_iommuv2_restore_nonsec()
176 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv2_restore_nonsec()
177 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv2_restore_nonsec()
179 prefetch = etnaviv_buffer_config_mmuv2(gpu, in etnaviv_iommuv2_restore_nonsec()
182 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_nonsec()
184 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_nonsec()
186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
189 static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_sec() argument
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/linux/drivers/gpu/drm/msm/
H A Dmsm_gpu.c26 static int enable_pwrrail(struct msm_gpu *gpu) in enable_pwrrail() argument
28 struct drm_device *dev = gpu->dev; in enable_pwrrail()
31 if (gpu->gpu_reg) { in enable_pwrrail()
32 ret = regulator_enable(gpu->gpu_reg); in enable_pwrrail()
39 if (gpu->gpu_cx) { in enable_pwrrail()
40 ret = regulator_enable(gpu->gpu_cx); in enable_pwrrail()
50 static int disable_pwrrail(struct msm_gpu *gpu) in disable_pwrrail() argument
52 if (gpu->gpu_cx) in disable_pwrrail()
53 regulator_disable(gpu->gpu_cx); in disable_pwrrail()
54 if (gpu->gpu_reg) in disable_pwrrail()
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H A Dmsm_gpu.h50 int (*get_param)(struct msm_gpu *gpu, struct msm_context *ctx,
52 int (*set_param)(struct msm_gpu *gpu, struct msm_context *ctx,
54 int (*hw_init)(struct msm_gpu *gpu);
59 int (*ucode_load)(struct msm_gpu *gpu);
61 int (*pm_suspend)(struct msm_gpu *gpu);
62 int (*pm_resume)(struct msm_gpu *gpu);
63 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
64 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
66 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
67 void (*recover)(struct msm_gpu *gpu);
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H A Dmsm_ringbuffer.c18 struct msm_gpu *gpu = submit->gpu; in msm_job_run() local
19 struct drm_device *dev = gpu->dev; in msm_job_run()
38 mutex_lock(&gpu->lock); in msm_job_run()
43 msm_gpu_submit(gpu, submit); in msm_job_run()
47 mutex_unlock(&gpu->lock); in msm_job_run()
65 struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, in msm_ringbuffer_new() argument
73 .dev = gpu->dev->dev, in msm_ringbuffer_new()
88 ring->gpu = gpu; in msm_ringbuffer_new()
91 ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ, in msm_ringbuffer_new()
92 check_apriv(gpu, MSM_BO_WC | MSM_BO_GPU_READONLY), in msm_ringbuffer_new()
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/linux/drivers/gpu/drm/msm/adreno/
H A Da8xx_gpu.c19 static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) in a8xx_aperture_slice_set() argument
21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a8xx_aperture_slice_set()
30 gpu_write(gpu, REG_A8XX_CP_APERTURE_CNTL_HOST, val); in a8xx_aperture_slice_set()
35 static void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) in a8xx_aperture_acquire() argument
37 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a8xx_aperture_acquire()
42 a8xx_aperture_slice_set(gpu, pipe, 0); in a8xx_aperture_acquire()
45 static void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags) in a8xx_aperture_release() argument
47 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a8xx_aperture_release()
53 static void a8xx_aperture_clear(struct msm_gpu *gpu) in a8xx_aperture_clear() argument
57 a8xx_aperture_acquire(gpu, PIPE_NONE, &flags); in a8xx_aperture_clear()
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H A Dadreno_gpu.h38 * so it helps to be able to group the GPU devices by generation and if
79 u64 (*get_timestamp)(struct msm_gpu *gpu);
217 * of gpu firmware to linux-firmware, the fw files were
243 * GPU specific offsets will be exported by GPU specific
281 static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu) in adreno_patchid() argument
287 WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1); in adreno_patchid()
288 return gpu->chip_id & 0xff; in adreno_patchid()
291 static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn) in adreno_is_revn() argument
293 if (WARN_ON_ONCE(!gpu->info)) in adreno_is_revn()
295 return gpu->info->revn == revn; in adreno_is_revn()
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H A Da3xx_gpu.c30 static void a3xx_dump(struct msm_gpu *gpu);
31 static bool a3xx_idle(struct msm_gpu *gpu);
33 static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a3xx_submit() argument
71 /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */ in a3xx_submit()
84 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_submit()
87 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init() argument
89 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
110 adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR); in a3xx_me_init()
111 return a3xx_idle(gpu); in a3xx_me_init()
114 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init() argument
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H A Da5xx_gpu.c17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr() argument
23 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in update_shadow_rptr()
33 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument
36 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
46 update_shadow_rptr(gpu, ring); in a5xx_flush()
63 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
66 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit_in_rb() argument
68 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_submit_in_rb()
115 a5xx_flush(gpu, ring, true); in a5xx_submit_in_rb()
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H A Da6xx_gpu.c19 static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu) in a6xx_gmu_get_timestamp() argument
21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gmu_get_timestamp()
40 static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 status, u32 mask) in fence_status_check() argument
49 gpu_write(gpu, offset, value); in fence_status_check()
61 struct msm_gpu *gpu = &adreno_gpu->base; in fenced_write() local
65 gpu_write(gpu, offset, value); in fenced_write()
77 fence_status_check(gpu, offset, value, status, mask), 0, 1000)) in fenced_write()
81 gpu_write(gpu, offset, value); in fenced_write()
85 fence_status_check(gpu, offset, value, status, mask), 0, 1000)) { in fenced_write()
88 * warning will allow gpu to move to power collapse which in fenced_write()
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H A Dadreno_device.c16 MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off…
24 MODULE_PARM_DESC(disable_acd, "Forcefully disable GPU ACD");
28 MODULE_PARM_DESC(skip_gpu, "Disable GPU driver register (0=enable GPU driver register (default), 1=…
51 /* identify gpu: */ in adreno_info()
72 struct msm_gpu *gpu = NULL; in adreno_load_gpu() local
77 gpu = dev_to_gpu(&pdev->dev); in adreno_load_gpu()
79 if (!gpu) { in adreno_load_gpu()
80 dev_err_once(dev->dev, "no GPU device was found\n"); in adreno_load_gpu()
84 adreno_gpu = to_adreno_gpu(gpu); in adreno_load_gpu()
96 if (gpu->funcs->ucode_load) { in adreno_load_gpu()
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H A Da5xx_preempt.c25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in get_next_ring()
63 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
65 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
68 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); in get_next_ring()
84 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer() local
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H A Da6xx_gpu_state.c133 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init() argument
136 dumper->ptr = msm_gem_kernel_new(gpu->dev, in a6xx_crashdumper_init()
137 SZ_1M, MSM_BO_WC, gpu->vm, in a6xx_crashdumper_init()
146 static int a6xx_crashdumper_run(struct msm_gpu *gpu, in a6xx_crashdumper_run() argument
149 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_crashdumper_run()
163 gpu_write64(gpu, REG_A6XX_CP_CRASH_DUMP_SCRIPT_BASE, dumper->iova); in a6xx_crashdumper_run()
165 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
167 ret = gpu_poll_timeout(gpu, REG_A6XX_CP_CRASH_DUMP_STATUS, val, in a6xx_crashdumper_run()
170 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
176 static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, in debugbus_read() argument
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H A Dadreno_gpu.c26 MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space");
31 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt() argument
34 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt()
85 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev); in zap_shader_load_mdt()
90 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); in zap_shader_load_mdt()
140 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) { in zap_shader_load_mdt()
176 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) in adreno_zap_shader_load() argument
178 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in adreno_zap_shader_load()
184 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); in adreno_zap_shader_load()
188 adreno_create_vm(struct msm_gpu *gpu, in adreno_create_vm() argument
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/linux/sound/hda/codecs/hdmi/
H A Dnvhdmi.c145 HDA_CODEC_ID_MODEL(0x10de0008, "GPU 08 HDMI/DP", MODEL_LEGACY),
146 HDA_CODEC_ID_MODEL(0x10de0009, "GPU 09 HDMI/DP", MODEL_LEGACY),
147 HDA_CODEC_ID_MODEL(0x10de000a, "GPU 0a HDMI/DP", MODEL_LEGACY),
148 HDA_CODEC_ID_MODEL(0x10de000b, "GPU 0b HDMI/DP", MODEL_LEGACY),
150 HDA_CODEC_ID_MODEL(0x10de000d, "GPU 0d HDMI/DP", MODEL_LEGACY),
151 HDA_CODEC_ID_MODEL(0x10de0010, "GPU 10 HDMI/DP", MODEL_LEGACY),
152 HDA_CODEC_ID_MODEL(0x10de0011, "GPU 11 HDMI/DP", MODEL_LEGACY),
153 HDA_CODEC_ID_MODEL(0x10de0012, "GPU 12 HDMI/DP", MODEL_LEGACY),
154 HDA_CODEC_ID_MODEL(0x10de0013, "GPU 13 HDMI/DP", MODEL_LEGACY),
155 HDA_CODEC_ID_MODEL(0x10de0014, "GPU 14 HDMI/DP", MODEL_LEGACY),
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/linux/drivers/gpu/drm/panthor/
H A Dpanthor_gpu.c29 * struct panthor_gpu - GPU block management data.
35 /** @irq: GPU irq. */
41 /** @pending_reqs: Pending GPU requests. */
44 /** @reqs_acked: GPU request wait queue. */
62 gpu_write(ptdev->gpu->iomem, GPU_COHERENCY_PROTOCOL, in panthor_gpu_coherency_set()
68 struct panthor_gpu *gpu = ptdev->gpu; in panthor_gpu_l2_config_set() local
82 gpu_write(gpu->iomem, GPU_ASN_HASH(i), data->asn_hash[i]); in panthor_gpu_l2_config_set()
84 l2_config = gpu_read(gpu->iomem, GPU_L2_CONFIG); in panthor_gpu_l2_config_set()
86 gpu_write(gpu->iomem, GPU_L2_CONFIG, l2_config); in panthor_gpu_l2_config_set()
91 struct panthor_gpu *gpu = ptdev->gpu; in panthor_gpu_irq_handler() local
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/linux/tools/testing/selftests/vfio/lib/drivers/nv_falcon/
H A Dnv_falcon.c72 static inline u32 gpu_read32(struct gpu_device *gpu, u32 offset) in gpu_read32() argument
74 return readl(gpu->bar0 + offset); in gpu_read32()
77 static inline void gpu_write32(struct gpu_device *gpu, u32 offset, u32 value) in gpu_write32() argument
79 writel(value, gpu->bar0 + offset); in gpu_write32()
96 struct gpu_device *gpu = to_gpu_device(device); in gpu_poll_register() local
104 value = gpu_read32(gpu, offset); in gpu_poll_register()
126 struct gpu_device *gpu = to_gpu_device(device); in fsp_poll_queue() local
134 head = gpu_read32(gpu, head_reg); in fsp_poll_queue()
135 tail = gpu_read32(gpu, tail_reg); in fsp_poll_queue()
156 struct gpu_device *gpu = to_gpu_device(device); in fsp_emem_write() local
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/linux/Documentation/devicetree/bindings/display/msm/
H A Dgpu.yaml5 $id: http://devicetree.org/schemas/display/msm/gpu.yaml#
36 figure out the gpu-id and patch level.
42 figure out the gpu-id and patch level.
107 help bring the GPU out of secure mode.
130 control the power for the GPU.
155 description: GPU Core clock
157 description: GPU Interface clock
159 description: GPU Memory Interface clock
175 description: GPU Core clock
177 description: GPU Interface clock
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H A Dgmu.yaml16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
112 - description: GPU CX clock
113 - description: GPU AXI clock
114 - description: GPU MEMNOC clock
143 - description: GPU CX clock
144 - description: GPU AXI clock
145 - description: GPU MEMNOC clock
146 - description: GPU AHB clock
147 - description: GPU HUB CX clock
180 - description: GPU CX clock
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/linux/Documentation/gpu/rfc/
H A Dgpusvm.rst4 GPU SVM Section
25 * Eviction is defined as migrating data from the GPU back to the
26 CPU without a virtual address to free up GPU memory.
32 * GPU page table invalidation, which requires a GPU virtual address, is
33 handled via the notifier that has access to the GPU virtual address.
34 * GPU fault side
36 and should strive to take mmap_read lock only in GPU SVM layer.
37 * Big retry loop to handle all races with the mmu notifier under the gpu
47 migration policy requiring GPU access to occur in GPU memory.
49 While no current user (Xe) of GPU SVM has such a policy, it is likely
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/linux/Documentation/driver-api/
H A Dedac.rst116 Several stacks of HBM chips connect to the CPU or GPU through an ultra-fast
196 GPU nodes can be accessed the same way as the data fabric on CPU nodes.
199 and each GPU data fabric contains four Unified Memory Controllers (UMC).
207 Memory controllers on AMD GPU nodes can be represented in EDAC thusly:
209 GPU DF / GPU Node -> EDAC MC
210 GPU UMC -> EDAC CSROW
211 GPU UMC channel -> EDAC CHANNEL
218 - The CPU UMC (Unified Memory Controller) is mostly the same as the GPU UMC.
224 - GPU UMCs use 1 chip select, So UMC = EDAC CSROW.
225 - GPU UMCs use 8 channels, So UMC channel = EDAC channel.
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/linux/Documentation/gpu/
H A Dvc4.rst5 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_drv.c
18 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_crtc.c
24 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_hvs.c
30 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_plane.c
36 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_hdmi.c
42 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_dsi.c
48 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_dpi.c
54 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_vec.c
69 --kunitconfig=drivers/gpu/drm/vc4/tests/.kunitconfig \
81 GPU buffer object (BO) management
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/linux/include/linux/
H A Dadreno-smmu-priv.h22 * This struct passes back key page fault information to the GPU driver
24 * The GPU driver can use this information to print informative
25 * log messages and provide deeper GPU specific insight into the fault.
38 * struct adreno_smmu_priv - private interface between adreno-smmu and GPU
46 * @get_fault_info: Called by the GPU fault handler to get information about
49 * stalling on fault is enabled, the GPU driver must call
53 * @set_prr_bit: [optional] Configure the GPU's Partially Resident
56 * the physical address of PRR page passed from GPU
59 * The GPU driver (drm/msm) and adreno-smmu work together for controlling
60 * the GPU's SMMU instance. This is by necessity, as the GPU is directly
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/linux/drivers/power/sequencing/
H A Dpwrseq-thead-gpu.c3 * T-HEAD TH1520 GPU Power Sequencer Driver
9 * GPU on the T-HEAD TH1520 SoC. The sequence requires coordinating resources
10 * from both the sequencer's parent device node (clkgen_reset) and the GPU's
13 * The `match` function is used to acquire the GPU's resources when the
14 * GPU driver requests the "gpu-power" sequence target.
59 * de-asserting the GPU reset. Assuming a worst-case scenario with in pwrseq_thead_gpu_enable()
60 * a very high GPU clock frequency, a delay of 1 microsecond is in pwrseq_thead_gpu_enable()
62 * feasible GPU clock speeds. in pwrseq_thead_gpu_enable()
102 .name = "gpu-power-sequence",
108 .name = "gpu-power",
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