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/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c34 { .name = "etnaviv-gpu,2d" },
42 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
44 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
48 *value = gpu->identity.model; in etnaviv_gpu_get_param()
52 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
56 *value = gpu->identity.features; in etnaviv_gpu_get_param()
60 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
64 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
68 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
72 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
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H A Detnaviv_gpu.h90 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
170 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() argument
172 writel(data, gpu->mmio + reg); in gpu_write()
175 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() argument
182 readl(gpu->mmio + reg); in gpu_read()
184 return readl(gpu->mmio + reg); in gpu_read()
187 static inline u32 gpu_fix_power_address(struct etnaviv_gpu *gpu, u32 reg) in gpu_fix_power_address() argument
190 if (gpu->identity.model == chipModel_GC300 && in gpu_fix_power_address()
191 gpu->identity.revision < 0x2000) in gpu_fix_power_address()
197 static inline void gpu_write_power(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write_power() argument
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H A Detnaviv_drv.c51 struct etnaviv_gpu *g = priv->gpu[i]; in load_gpu()
58 priv->gpu[i] = NULL; in load_gpu()
86 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_open() local
89 if (gpu) { in etnaviv_open()
90 sched = &gpu->sched; in etnaviv_open()
113 struct etnaviv_gpu *gpu = priv->gpu[i]; in etnaviv_postclose() local
115 if (gpu) in etnaviv_postclose()
151 static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m) in etnaviv_mmu_show() argument
156 seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev)); in etnaviv_mmu_show()
159 * Lock the GPU to avoid a MMU context switch just now and elevate in etnaviv_mmu_show()
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H A Detnaviv_iommu_v2.c165 static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_nonsec() argument
172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
175 if (gpu->mmu_context) in etnaviv_iommuv2_restore_nonsec()
176 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv2_restore_nonsec()
177 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv2_restore_nonsec()
179 prefetch = etnaviv_buffer_config_mmuv2(gpu, in etnaviv_iommuv2_restore_nonsec()
182 etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer), in etnaviv_iommuv2_restore_nonsec()
184 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_iommuv2_restore_nonsec()
186 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
189 static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu, in etnaviv_iommuv2_restore_sec() argument
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H A Detnaviv_iommu.c89 static void etnaviv_iommuv1_restore(struct etnaviv_gpu *gpu, in etnaviv_iommuv1_restore() argument
95 if (gpu->mmu_context) in etnaviv_iommuv1_restore()
96 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_iommuv1_restore()
97 gpu->mmu_context = etnaviv_iommu_context_get(context); in etnaviv_iommuv1_restore()
100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
101 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
102 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
103 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
104 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
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H A Detnaviv_dump.c82 struct etnaviv_gpu *gpu) in etnaviv_core_dump_registers() argument
92 read_addr = gpu_fix_power_address(gpu, read_addr); in etnaviv_core_dump_registers()
94 reg->value = cpu_to_le32(gpu_read(gpu, read_addr)); in etnaviv_core_dump_registers()
120 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_core_dump() local
142 mmu_size + gpu->buffer.size + submit->cmdbuf.size; in etnaviv_core_dump()
165 dev_warn(gpu->dev, "failed to allocate devcoredump file\n"); in etnaviv_core_dump()
175 etnaviv_core_dump_registers(&iter, gpu); in etnaviv_core_dump()
177 etnaviv_core_dump_mem(&iter, ETDUMP_BUF_RING, gpu->buffer.vaddr, in etnaviv_core_dump()
178 gpu->buffer.size, in etnaviv_core_dump()
179 etnaviv_cmdbuf_get_va(&gpu->buffer, in etnaviv_core_dump()
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/linux/sound/hda/codecs/hdmi/
H A Dnvhdmi.c145 HDA_CODEC_ID_MODEL(0x10de0008, "GPU 08 HDMI/DP", MODEL_LEGACY),
146 HDA_CODEC_ID_MODEL(0x10de0009, "GPU 09 HDMI/DP", MODEL_LEGACY),
147 HDA_CODEC_ID_MODEL(0x10de000a, "GPU 0a HDMI/DP", MODEL_LEGACY),
148 HDA_CODEC_ID_MODEL(0x10de000b, "GPU 0b HDMI/DP", MODEL_LEGACY),
150 HDA_CODEC_ID_MODEL(0x10de000d, "GPU 0d HDMI/DP", MODEL_LEGACY),
151 HDA_CODEC_ID_MODEL(0x10de0010, "GPU 10 HDMI/DP", MODEL_LEGACY),
152 HDA_CODEC_ID_MODEL(0x10de0011, "GPU 11 HDMI/DP", MODEL_LEGACY),
153 HDA_CODEC_ID_MODEL(0x10de0012, "GPU 12 HDMI/DP", MODEL_LEGACY),
154 HDA_CODEC_ID_MODEL(0x10de0013, "GPU 13 HDMI/DP", MODEL_LEGACY),
155 HDA_CODEC_ID_MODEL(0x10de0014, "GPU 14 HDMI/DP", MODEL_LEGACY),
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/linux/drivers/gpu/drm/panthor/
H A Dpanthor_gpu.c29 * struct panthor_gpu - GPU block management data.
35 /** @irq: GPU irq. */
41 /** @pending_reqs: Pending GPU requests. */
44 /** @reqs_acked: GPU request wait queue. */
62 gpu_write(ptdev->gpu->iomem, GPU_COHERENCY_PROTOCOL, in panthor_gpu_coherency_set()
68 struct panthor_gpu *gpu = ptdev->gpu; in panthor_gpu_l2_config_set() local
82 gpu_write(gpu->iomem, GPU_ASN_HASH(i), data->asn_hash[i]); in panthor_gpu_l2_config_set()
84 l2_config = gpu_read(gpu->iomem, GPU_L2_CONFIG); in panthor_gpu_l2_config_set()
86 gpu_write(gpu->iomem, GPU_L2_CONFIG, l2_config); in panthor_gpu_l2_config_set()
91 struct panthor_gpu *gpu = ptdev->gpu; in panthor_gpu_irq_handler() local
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/linux/tools/testing/selftests/vfio/lib/drivers/nv_falcon/
H A Dnv_falcon.c72 static inline u32 gpu_read32(struct gpu_device *gpu, u32 offset) in gpu_read32() argument
74 return readl(gpu->bar0 + offset); in gpu_read32()
77 static inline void gpu_write32(struct gpu_device *gpu, u32 offset, u32 value) in gpu_write32() argument
79 writel(value, gpu->bar0 + offset); in gpu_write32()
96 struct gpu_device *gpu = to_gpu_device(device); in gpu_poll_register() local
104 value = gpu_read32(gpu, offset); in gpu_poll_register()
126 struct gpu_device *gpu = to_gpu_device(device); in fsp_poll_queue() local
134 head = gpu_read32(gpu, head_reg); in fsp_poll_queue()
135 tail = gpu_read32(gpu, tail_reg); in fsp_poll_queue()
156 struct gpu_device *gpu = to_gpu_device(device); in fsp_emem_write() local
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/linux/drivers/gpu/drm/msm/adreno/
H A Da5xx_preempt.c25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in get_next_ring()
63 for (i = 0; i < gpu->nr_rings; i++) { in get_next_ring()
65 struct msm_ringbuffer *ring = gpu->rb[i]; in get_next_ring()
68 empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring)); in get_next_ring()
84 struct msm_gpu *gpu = &a5xx_gpu->base.base; in a5xx_preempt_timer() local
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H A Da5xx_gpu.h54 void a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor);
106 * @counter: GPU address of the storage area for the performance counters
138 int a5xx_power_init(struct msm_gpu *gpu);
139 void a5xx_gpmu_ucode_init(struct msm_gpu *gpu);
141 static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs, in spin_usecs() argument
146 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
157 bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
158 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state);
160 void a5xx_preempt_init(struct msm_gpu *gpu);
161 void a5xx_preempt_hw_init(struct msm_gpu *gpu);
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/linux/drivers/gpu/drm/
H A Ddrm_gpusvm.c25 * GPU Shared Virtual Memory (GPU SVM) layer for the Direct Rendering Manager (DRM)
27 * between the CPU and GPU. It enables efficient data exchange and processing
28 * for GPU-accelerated applications by allowing memory sharing and
29 * synchronization between the CPU's and GPU's virtual address spaces.
31 * Key GPU SVM Components:
34 * Used for tracking memory intervals and notifying the GPU of changes,
35 * notifiers are sized based on a GPU SVM initialization parameter, with a
38 * tracked within a GPU SVM Red-BlacK tree and list and are dynamically
42 * Represent memory ranges mapped in a DRM device and managed by GPU SVM.
43 * They are sized based on an array of chunk sizes, which is a GPU SVM
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/linux/Documentation/gpu/rfc/
H A Dgpusvm.rst4 GPU SVM Section
25 * Eviction is defined as migrating data from the GPU back to the
26 CPU without a virtual address to free up GPU memory.
32 * GPU page table invalidation, which requires a GPU virtual address, is
33 handled via the notifier that has access to the GPU virtual address.
34 * GPU fault side
36 and should strive to take mmap_read lock only in GPU SVM layer.
37 * Big retry loop to handle all races with the mmu notifier under the gpu
47 migration policy requiring GPU access to occur in GPU memory.
49 While no current user (Xe) of GPU SVM has such a policy, it is likely
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/linux/Documentation/devicetree/bindings/gpu/
H A Dimg,powervr-sgx.yaml6 $id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml#
19 - ti,omap3430-gpu # Rev 121
20 - ti,omap3630-gpu # Rev 125
24 - ingenic,jz4780-gpu # Rev 130
25 - ti,omap4430-gpu # Rev 120
29 - allwinner,sun6i-a31-gpu # MP2 Rev 115
30 - ti,omap4470-gpu # MP1 Rev 112
31 - ti,omap5432-gpu # MP2 Rev 105
32 - ti,am5728-gpu # MP2 Rev 116
33 - ti,am6548-gpu # MP1 Rev 117
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H A Dvivante,gc.yaml4 $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
7 title: Vivante GPU
9 description: Vivante GPU core devices
34 - description: GPU core clock
35 - description: Shader clock (only required if GPU has feature PIPE_3D)
36 - description: AHB/slave interface clock (only required if GPU can gate
65 gpu@130000 {
/linux/Documentation/driver-api/
H A Dedac.rst116 Several stacks of HBM chips connect to the CPU or GPU through an ultra-fast
196 GPU nodes can be accessed the same way as the data fabric on CPU nodes.
199 and each GPU data fabric contains four Unified Memory Controllers (UMC).
207 Memory controllers on AMD GPU nodes can be represented in EDAC thusly:
209 GPU DF / GPU Node -> EDAC MC
210 GPU UMC -> EDAC CSROW
211 GPU UMC channel -> EDAC CHANNEL
218 - The CPU UMC (Unified Memory Controller) is mostly the same as the GPU UMC.
224 - GPU UMCs use 1 chip select, So UMC = EDAC CSROW.
225 - GPU UMCs use 8 channels, So UMC channel = EDAC channel.
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/linux/Documentation/gpu/
H A Dvc4.rst5 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_drv.c
18 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_crtc.c
24 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_hvs.c
30 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_plane.c
36 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_hdmi.c
42 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_dsi.c
48 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_dpi.c
54 .. kernel-doc:: drivers/gpu/drm/vc4/vc4_vec.c
69 --kunitconfig=drivers/gpu/drm/vc4/tests/.kunitconfig \
81 GPU buffer object (BO) management
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H A Dv3d.rst5 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_drv.c
8 GPU buffer object (BO) management
11 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_bo.c
16 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_mmu.c
19 GPU Scheduling
21 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_sched.c
27 .. kernel-doc:: drivers/gpu/drm/v3d/v3d_irq.c
/linux/include/linux/
H A Dadreno-smmu-priv.h22 * This struct passes back key page fault information to the GPU driver
24 * The GPU driver can use this information to print informative
25 * log messages and provide deeper GPU specific insight into the fault.
38 * struct adreno_smmu_priv - private interface between adreno-smmu and GPU
46 * @get_fault_info: Called by the GPU fault handler to get information about
49 * stalling on fault is enabled, the GPU driver must call
53 * @set_prr_bit: [optional] Configure the GPU's Partially Resident
56 * the physical address of PRR page passed from GPU
59 * The GPU driver (drm/msm) and adreno-smmu work together for controlling
60 * the GPU's SMMU instance. This is by necessity, as the GPU is directly
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/linux/drivers/power/sequencing/
H A Dpwrseq-thead-gpu.c3 * T-HEAD TH1520 GPU Power Sequencer Driver
9 * GPU on the T-HEAD TH1520 SoC. The sequence requires coordinating resources
10 * from both the sequencer's parent device node (clkgen_reset) and the GPU's
13 * The `match` function is used to acquire the GPU's resources when the
14 * GPU driver requests the "gpu-power" sequence target.
59 * de-asserting the GPU reset. Assuming a worst-case scenario with in pwrseq_thead_gpu_enable()
60 * a very high GPU clock frequency, a delay of 1 microsecond is in pwrseq_thead_gpu_enable()
62 * feasible GPU clock speeds. in pwrseq_thead_gpu_enable()
102 .name = "gpu-power-sequence",
108 .name = "gpu-power",
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/linux/Documentation/gpu/nova/core/
H A Ddevinit.rst7 overview using the Ampere GPU family as an example. The goal is to provide a conceptual
11 that occur after a GPU reset. The devinit sequence is essential for properly configuring
12 the GPU hardware before it can be used.
15 Unit) microcontroller of the GPU. This interpreter executes a "script" of initialization
18 nova-core driver is even loaded. On an Ampere GPU, the devinit ucode is separate from the
33 Upon reset, several microcontrollers on the GPU (such as PMU, SEC2, GSP, etc.) run GPU
34 firmware (gfw) code to set up the GPU and its core parameters. Most of the GPU is
37 These low-level GPU firmware components are typically:
43 - On an Ampere GPU, the FWSEC typically runs on the GSP (GPU System Processor) in
/linux/drivers/gpu/drm/i915/gvt/
H A Dvgpu.c82 * vGPU type name is defined as GVTg_Vx_y which contains the physical GPU
87 * vGPU on same physical GPU depending on available resource. Each vGPU
164 * intel_gvt_activate_vgpu - activate a virtual GPU
165 * @vgpu: virtual GPU
167 * This function is called when user wants to activate a virtual GPU.
176 * intel_gvt_deactivate_vgpu - deactivate a virtual GPU
177 * @vgpu: virtual GPU
179 * This function is called when user wants to deactivate a virtual GPU.
180 * The virtual GPU will be stopped.
201 * intel_gvt_release_vgpu - release a virtual GPU
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/linux/drivers/gpu/drm/radeon/
H A Dradeon_atpx_handler.c266 * radeon_atpx_set_discrete_state - power up/down discrete GPU
269 * @state: discrete GPU state (0 = power down, 1 = power up)
272 * power down/up the discrete GPU (all asics).
304 * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
307 * switch the display mux between the discrete GPU and integrated GPU
336 * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
339 * switch the i2c/hpd mux between the discrete GPU and integrated GPU
365 * radeon_atpx_switch_start - notify the sbios of a GPU switch
368 * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
371 * function to notify the sbios that a switch between the discrete GPU and
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/linux/Documentation/gpu/amdgpu/display/
H A Ddisplay-manager.rst8 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
17 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
20 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
26 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
47 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
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/linux/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c15 * GFX PLL is the PLL used by DC, GMC and GPU, the structure of the GFX PLL
26 * | +----| / div_out_2 | _____/ _____ GPU
37 unsigned div_out_gpu : 7; /* 20 : 14 GPU output clock divider */
46 unsigned sel_out_gpu : 1; /* 42 gpu output clk enable */
83 unsigned int *gpu) in loongson_gfxpll_get_rates() argument
113 if (gpu) in loongson_gfxpll_get_rates()
114 *gpu = gpu_mhz; in loongson_gfxpll_get_rates()
122 unsigned int dc, gmc, gpu; in loongson_gfxpll_print() local
134 this->funcs->get_rates(this, &dc, &gmc, &gpu); in loongson_gfxpll_print()
136 drm_printf(p, "dc: %uMHz, gmc: %uMHz, gpu: %uMHz\n", dc, gmc, gpu); in loongson_gfxpll_print()
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