Lines Matching full:gpu
32 { .name = "etnaviv-gpu,2d" },
40 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) in etnaviv_gpu_get_param() argument
42 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
46 *value = gpu->identity.model; in etnaviv_gpu_get_param()
50 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
54 *value = gpu->identity.features; in etnaviv_gpu_get_param()
58 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
62 *value = gpu->identity.minor_features1; in etnaviv_gpu_get_param()
66 *value = gpu->identity.minor_features2; in etnaviv_gpu_get_param()
70 *value = gpu->identity.minor_features3; in etnaviv_gpu_get_param()
74 *value = gpu->identity.minor_features4; in etnaviv_gpu_get_param()
78 *value = gpu->identity.minor_features5; in etnaviv_gpu_get_param()
82 *value = gpu->identity.minor_features6; in etnaviv_gpu_get_param()
86 *value = gpu->identity.minor_features7; in etnaviv_gpu_get_param()
90 *value = gpu->identity.minor_features8; in etnaviv_gpu_get_param()
94 *value = gpu->identity.minor_features9; in etnaviv_gpu_get_param()
98 *value = gpu->identity.minor_features10; in etnaviv_gpu_get_param()
102 *value = gpu->identity.minor_features11; in etnaviv_gpu_get_param()
106 *value = gpu->identity.stream_count; in etnaviv_gpu_get_param()
110 *value = gpu->identity.register_max; in etnaviv_gpu_get_param()
114 *value = gpu->identity.thread_count; in etnaviv_gpu_get_param()
118 *value = gpu->identity.vertex_cache_size; in etnaviv_gpu_get_param()
122 *value = gpu->identity.shader_core_count; in etnaviv_gpu_get_param()
126 *value = gpu->identity.pixel_pipes; in etnaviv_gpu_get_param()
130 *value = gpu->identity.vertex_output_buffer_size; in etnaviv_gpu_get_param()
134 *value = gpu->identity.buffer_size; in etnaviv_gpu_get_param()
138 *value = gpu->identity.instruction_count; in etnaviv_gpu_get_param()
142 *value = gpu->identity.num_constants; in etnaviv_gpu_get_param()
146 *value = gpu->identity.varyings_count; in etnaviv_gpu_get_param()
157 *value = gpu->identity.product_id; in etnaviv_gpu_get_param()
161 *value = gpu->identity.customer_id; in etnaviv_gpu_get_param()
165 *value = gpu->identity.eco_id; in etnaviv_gpu_get_param()
169 DBG("%s: invalid param: %u", dev_name(gpu->dev), param); in etnaviv_gpu_get_param()
176 static int etnaviv_gpu_reset_deassert(struct etnaviv_gpu *gpu) in etnaviv_gpu_reset_deassert() argument
186 ret = reset_control_deassert(gpu->rst); in etnaviv_gpu_reset_deassert()
199 static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision) in etnaviv_is_model_rev() argument
201 return gpu->identity.model == model && in etnaviv_is_model_rev()
202 gpu->identity.revision == revision; in etnaviv_is_model_rev()
208 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) in etnaviv_hw_specs() argument
210 if (gpu->identity.minor_features0 & in etnaviv_hw_specs()
215 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
216 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); in etnaviv_hw_specs()
217 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); in etnaviv_hw_specs()
218 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); in etnaviv_hw_specs()
220 gpu->identity.stream_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
222 gpu->identity.register_max = etnaviv_field(specs[0], in etnaviv_hw_specs()
224 gpu->identity.thread_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
226 gpu->identity.vertex_cache_size = etnaviv_field(specs[0], in etnaviv_hw_specs()
228 gpu->identity.shader_core_count = etnaviv_field(specs[0], in etnaviv_hw_specs()
230 gpu->identity.pixel_pipes = etnaviv_field(specs[0], in etnaviv_hw_specs()
232 gpu->identity.vertex_output_buffer_size = in etnaviv_hw_specs()
236 gpu->identity.buffer_size = etnaviv_field(specs[1], in etnaviv_hw_specs()
238 gpu->identity.instruction_count = etnaviv_field(specs[1], in etnaviv_hw_specs()
240 gpu->identity.num_constants = etnaviv_field(specs[1], in etnaviv_hw_specs()
243 gpu->identity.varyings_count = etnaviv_field(specs[2], in etnaviv_hw_specs()
250 gpu->identity.stream_count = streams; in etnaviv_hw_specs()
254 if (gpu->identity.stream_count == 0) { in etnaviv_hw_specs()
255 if (gpu->identity.model >= 0x1000) in etnaviv_hw_specs()
256 gpu->identity.stream_count = 4; in etnaviv_hw_specs()
258 gpu->identity.stream_count = 1; in etnaviv_hw_specs()
262 if (gpu->identity.register_max) in etnaviv_hw_specs()
263 gpu->identity.register_max = 1 << gpu->identity.register_max; in etnaviv_hw_specs()
264 else if (gpu->identity.model == chipModel_GC400) in etnaviv_hw_specs()
265 gpu->identity.register_max = 32; in etnaviv_hw_specs()
267 gpu->identity.register_max = 64; in etnaviv_hw_specs()
270 if (gpu->identity.thread_count) in etnaviv_hw_specs()
271 gpu->identity.thread_count = 1 << gpu->identity.thread_count; in etnaviv_hw_specs()
272 else if (gpu->identity.model == chipModel_GC400) in etnaviv_hw_specs()
273 gpu->identity.thread_count = 64; in etnaviv_hw_specs()
274 else if (gpu->identity.model == chipModel_GC500 || in etnaviv_hw_specs()
275 gpu->identity.model == chipModel_GC530) in etnaviv_hw_specs()
276 gpu->identity.thread_count = 128; in etnaviv_hw_specs()
278 gpu->identity.thread_count = 256; in etnaviv_hw_specs()
280 if (gpu->identity.vertex_cache_size == 0) in etnaviv_hw_specs()
281 gpu->identity.vertex_cache_size = 8; in etnaviv_hw_specs()
283 if (gpu->identity.shader_core_count == 0) { in etnaviv_hw_specs()
284 if (gpu->identity.model >= 0x1000) in etnaviv_hw_specs()
285 gpu->identity.shader_core_count = 2; in etnaviv_hw_specs()
287 gpu->identity.shader_core_count = 1; in etnaviv_hw_specs()
290 if (gpu->identity.pixel_pipes == 0) in etnaviv_hw_specs()
291 gpu->identity.pixel_pipes = 1; in etnaviv_hw_specs()
294 if (gpu->identity.vertex_output_buffer_size) { in etnaviv_hw_specs()
295 gpu->identity.vertex_output_buffer_size = in etnaviv_hw_specs()
296 1 << gpu->identity.vertex_output_buffer_size; in etnaviv_hw_specs()
297 } else if (gpu->identity.model == chipModel_GC400) { in etnaviv_hw_specs()
298 if (gpu->identity.revision < 0x4000) in etnaviv_hw_specs()
299 gpu->identity.vertex_output_buffer_size = 512; in etnaviv_hw_specs()
300 else if (gpu->identity.revision < 0x4200) in etnaviv_hw_specs()
301 gpu->identity.vertex_output_buffer_size = 256; in etnaviv_hw_specs()
303 gpu->identity.vertex_output_buffer_size = 128; in etnaviv_hw_specs()
305 gpu->identity.vertex_output_buffer_size = 512; in etnaviv_hw_specs()
308 switch (gpu->identity.instruction_count) { in etnaviv_hw_specs()
310 if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || in etnaviv_hw_specs()
311 gpu->identity.model == chipModel_GC880) in etnaviv_hw_specs()
312 gpu->identity.instruction_count = 512; in etnaviv_hw_specs()
314 gpu->identity.instruction_count = 256; in etnaviv_hw_specs()
318 gpu->identity.instruction_count = 1024; in etnaviv_hw_specs()
322 gpu->identity.instruction_count = 2048; in etnaviv_hw_specs()
326 gpu->identity.instruction_count = 256; in etnaviv_hw_specs()
330 if (gpu->identity.num_constants == 0) in etnaviv_hw_specs()
331 gpu->identity.num_constants = 168; in etnaviv_hw_specs()
333 if (gpu->identity.varyings_count == 0) { in etnaviv_hw_specs()
334 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0) in etnaviv_hw_specs()
335 gpu->identity.varyings_count = 12; in etnaviv_hw_specs()
337 gpu->identity.varyings_count = 8; in etnaviv_hw_specs()
344 if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) || in etnaviv_hw_specs()
345 etnaviv_is_model_rev(gpu, 0x4000, 0x5222) || in etnaviv_hw_specs()
346 etnaviv_is_model_rev(gpu, 0x4000, 0x5245) || in etnaviv_hw_specs()
347 etnaviv_is_model_rev(gpu, 0x4000, 0x5208) || in etnaviv_hw_specs()
348 etnaviv_is_model_rev(gpu, 0x3000, 0x5435) || in etnaviv_hw_specs()
349 etnaviv_is_model_rev(gpu, 0x2200, 0x5244) || in etnaviv_hw_specs()
350 etnaviv_is_model_rev(gpu, 0x2100, 0x5108) || in etnaviv_hw_specs()
351 etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || in etnaviv_hw_specs()
352 etnaviv_is_model_rev(gpu, 0x1500, 0x5246) || in etnaviv_hw_specs()
353 etnaviv_is_model_rev(gpu, 0x880, 0x5107) || in etnaviv_hw_specs()
354 etnaviv_is_model_rev(gpu, 0x880, 0x5106)) in etnaviv_hw_specs()
355 gpu->identity.varyings_count -= 1; in etnaviv_hw_specs()
358 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) in etnaviv_hw_identify() argument
362 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); in etnaviv_hw_identify()
366 gpu->identity.model = chipModel_GC500; in etnaviv_hw_identify()
367 gpu->identity.revision = etnaviv_field(chipIdentity, in etnaviv_hw_identify()
370 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); in etnaviv_hw_identify()
372 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); in etnaviv_hw_identify()
373 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); in etnaviv_hw_identify()
374 gpu->identity.customer_id = gpu_read(gpu, VIVS_HI_CHIP_CUSTOMER_ID); in etnaviv_hw_identify()
380 if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) { in etnaviv_hw_identify()
381 gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); in etnaviv_hw_identify()
382 gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID); in etnaviv_hw_identify()
391 if ((gpu->identity.model & 0xff00) == 0x0400 && in etnaviv_hw_identify()
392 gpu->identity.model != chipModel_GC420) { in etnaviv_hw_identify()
393 gpu->identity.model = gpu->identity.model & 0x0400; in etnaviv_hw_identify()
397 if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) { in etnaviv_hw_identify()
398 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); in etnaviv_hw_identify()
405 gpu->identity.revision = 0x1051; in etnaviv_hw_identify()
410 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in in etnaviv_hw_identify()
416 if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) { in etnaviv_hw_identify()
417 gpu->identity.model = chipModel_GC3000; in etnaviv_hw_identify()
418 gpu->identity.revision &= 0xffff; in etnaviv_hw_identify()
421 if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617)) in etnaviv_hw_identify()
422 gpu->identity.eco_id = 1; in etnaviv_hw_identify()
424 if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511)) in etnaviv_hw_identify()
425 gpu->identity.eco_id = 1; in etnaviv_hw_identify()
428 dev_info(gpu->dev, "model: GC%x, revision: %x\n", in etnaviv_hw_identify()
429 gpu->identity.model, gpu->identity.revision); in etnaviv_hw_identify()
431 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP; in etnaviv_hw_identify()
436 if (etnaviv_fill_identity_from_hwdb(gpu)) in etnaviv_hw_identify()
439 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); in etnaviv_hw_identify()
442 if (gpu->identity.model == chipModel_GC700) in etnaviv_hw_identify()
443 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; in etnaviv_hw_identify()
446 if ((gpu->identity.model == chipModel_GC500 && in etnaviv_hw_identify()
447 gpu->identity.revision <= 2) || in etnaviv_hw_identify()
448 gpu->identity.model == chipModel_GC300) in etnaviv_hw_identify()
449 gpu->identity.features |= chipFeatures_PIPE_2D; in etnaviv_hw_identify()
451 if ((gpu->identity.model == chipModel_GC500 && in etnaviv_hw_identify()
452 gpu->identity.revision < 2) || in etnaviv_hw_identify()
453 (gpu->identity.model == chipModel_GC300 && in etnaviv_hw_identify()
454 gpu->identity.revision < 0x2000)) { in etnaviv_hw_identify()
460 gpu->identity.minor_features0 = 0; in etnaviv_hw_identify()
461 gpu->identity.minor_features1 = 0; in etnaviv_hw_identify()
462 gpu->identity.minor_features2 = 0; in etnaviv_hw_identify()
463 gpu->identity.minor_features3 = 0; in etnaviv_hw_identify()
464 gpu->identity.minor_features4 = 0; in etnaviv_hw_identify()
465 gpu->identity.minor_features5 = 0; in etnaviv_hw_identify()
467 gpu->identity.minor_features0 = in etnaviv_hw_identify()
468 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0); in etnaviv_hw_identify()
470 if (gpu->identity.minor_features0 & in etnaviv_hw_identify()
472 gpu->identity.minor_features1 = in etnaviv_hw_identify()
473 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1); in etnaviv_hw_identify()
474 gpu->identity.minor_features2 = in etnaviv_hw_identify()
475 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2); in etnaviv_hw_identify()
476 gpu->identity.minor_features3 = in etnaviv_hw_identify()
477 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3); in etnaviv_hw_identify()
478 gpu->identity.minor_features4 = in etnaviv_hw_identify()
479 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4); in etnaviv_hw_identify()
480 gpu->identity.minor_features5 = in etnaviv_hw_identify()
481 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5); in etnaviv_hw_identify()
485 if (gpu->identity.model == chipModel_GC600 || in etnaviv_hw_identify()
486 gpu->identity.model == chipModel_GC300) in etnaviv_hw_identify()
487 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX | in etnaviv_hw_identify()
496 etnaviv_hw_specs(gpu); in etnaviv_hw_identify()
499 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock) in etnaviv_gpu_load_clock() argument
501 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
503 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
506 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu) in etnaviv_gpu_update_clock() argument
508 if (gpu->identity.minor_features2 & in etnaviv_gpu_update_clock()
510 clk_set_rate(gpu->clk_core, in etnaviv_gpu_update_clock()
511 gpu->base_rate_core >> gpu->freq_scale); in etnaviv_gpu_update_clock()
512 clk_set_rate(gpu->clk_shader, in etnaviv_gpu_update_clock()
513 gpu->base_rate_shader >> gpu->freq_scale); in etnaviv_gpu_update_clock()
515 unsigned int fscale = 1 << (6 - gpu->freq_scale); in etnaviv_gpu_update_clock()
516 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_gpu_update_clock()
520 etnaviv_gpu_load_clock(gpu, clock); in etnaviv_gpu_update_clock()
526 * If the GPU base frequency is unknown use 200 wait cycles. in etnaviv_gpu_update_clock()
528 gpu->fe_waitcycles = clamp(gpu->base_rate_core >> (15 - gpu->freq_scale), in etnaviv_gpu_update_clock()
532 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu) in etnaviv_hw_reset() argument
538 /* We hope that the GPU resets in under one second */ in etnaviv_hw_reset()
542 unsigned int fscale = 1 << (6 - gpu->freq_scale); in etnaviv_hw_reset()
546 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, 0x0); in etnaviv_hw_reset()
550 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); in etnaviv_hw_reset()
552 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); in etnaviv_hw_reset()
556 etnaviv_gpu_load_clock(gpu, control); in etnaviv_hw_reset()
558 /* isolate the GPU. */ in etnaviv_hw_reset()
560 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
562 if (gpu->sec_mode == ETNA_SEC_KERNEL) { in etnaviv_hw_reset()
563 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
568 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
576 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
578 /* reset GPU isolation. */ in etnaviv_hw_reset()
580 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
583 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset()
587 dev_dbg(gpu->dev, "FE is not idle\n"); in etnaviv_hw_reset()
592 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_hw_reset()
594 /* is the GPU idle? */ in etnaviv_hw_reset()
597 dev_dbg(gpu->dev, "GPU is not idle\n"); in etnaviv_hw_reset()
603 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
610 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_hw_reset()
611 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in etnaviv_hw_reset()
613 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n", in etnaviv_hw_reset()
621 /* We rely on the GPU running, so program the clock */ in etnaviv_hw_reset()
622 etnaviv_gpu_update_clock(gpu); in etnaviv_hw_reset()
624 gpu->state = ETNA_GPU_STATE_RESET; in etnaviv_hw_reset()
625 gpu->exec_state = -1; in etnaviv_hw_reset()
626 if (gpu->mmu_context) in etnaviv_hw_reset()
627 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_hw_reset()
628 gpu->mmu_context = NULL; in etnaviv_hw_reset()
633 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) in etnaviv_gpu_enable_mlcg() argument
638 ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); in etnaviv_gpu_enable_mlcg()
642 if (gpu->identity.revision == 0x4301 || in etnaviv_gpu_enable_mlcg()
643 gpu->identity.revision == 0x4302) in etnaviv_gpu_enable_mlcg()
646 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc); in etnaviv_gpu_enable_mlcg()
648 pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS); in etnaviv_gpu_enable_mlcg()
651 if (gpu->identity.model >= chipModel_GC400 && in etnaviv_gpu_enable_mlcg()
652 gpu->identity.model != chipModel_GC420 && in etnaviv_gpu_enable_mlcg()
653 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12)) in etnaviv_gpu_enable_mlcg()
660 if (gpu->identity.revision < 0x5000 && in etnaviv_gpu_enable_mlcg()
661 gpu->identity.minor_features0 & chipMinorFeatures0_HZ && in etnaviv_gpu_enable_mlcg()
662 !(gpu->identity.minor_features1 & in etnaviv_gpu_enable_mlcg()
666 if (gpu->identity.revision < 0x5422) in etnaviv_gpu_enable_mlcg()
670 if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) || in etnaviv_gpu_enable_mlcg()
671 etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || in etnaviv_gpu_enable_mlcg()
672 etnaviv_is_model_rev(gpu, 0x7000, 0x6202) || in etnaviv_gpu_enable_mlcg()
673 etnaviv_is_model_rev(gpu, 0x7000, 0x6203)) in etnaviv_gpu_enable_mlcg()
677 if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202)) in etnaviv_gpu_enable_mlcg()
682 if (etnaviv_is_model_rev(gpu, 0x8000, 0x7200) || in etnaviv_gpu_enable_mlcg()
683 etnaviv_is_model_rev(gpu, 0x8000, 0x8002) || in etnaviv_gpu_enable_mlcg()
684 etnaviv_is_model_rev(gpu, 0x9200, 0x6304)) in etnaviv_gpu_enable_mlcg()
690 gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc); in etnaviv_gpu_enable_mlcg()
693 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch) in etnaviv_gpu_start_fe() argument
695 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); in etnaviv_gpu_start_fe()
696 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
700 if (gpu->sec_mode == ETNA_SEC_KERNEL) { in etnaviv_gpu_start_fe()
701 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
707 static void etnaviv_gpu_start_fe_idleloop(struct etnaviv_gpu *gpu, in etnaviv_gpu_start_fe_idleloop() argument
713 WARN_ON(gpu->state != ETNA_GPU_STATE_INITIALIZED); in etnaviv_gpu_start_fe_idleloop()
716 etnaviv_iommu_restore(gpu, context); in etnaviv_gpu_start_fe_idleloop()
719 prefetch = etnaviv_buffer_init(gpu); in etnaviv_gpu_start_fe_idleloop()
720 address = etnaviv_cmdbuf_get_va(&gpu->buffer, in etnaviv_gpu_start_fe_idleloop()
721 &gpu->mmu_context->cmdbuf_mapping); in etnaviv_gpu_start_fe_idleloop()
723 etnaviv_gpu_start_fe(gpu, address, prefetch); in etnaviv_gpu_start_fe_idleloop()
725 gpu->state = ETNA_GPU_STATE_RUNNING; in etnaviv_gpu_start_fe_idleloop()
728 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) in etnaviv_gpu_setup_pulse_eater() argument
736 if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) || in etnaviv_gpu_setup_pulse_eater()
737 etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) { in etnaviv_gpu_setup_pulse_eater()
742 if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) || in etnaviv_gpu_setup_pulse_eater()
743 etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) { in etnaviv_gpu_setup_pulse_eater()
748 if ((gpu->identity.revision > 0x5420) && in etnaviv_gpu_setup_pulse_eater()
749 (gpu->identity.features & chipFeatures_PIPE_3D)) in etnaviv_gpu_setup_pulse_eater()
752 pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER); in etnaviv_gpu_setup_pulse_eater()
756 gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater); in etnaviv_gpu_setup_pulse_eater()
759 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) in etnaviv_gpu_hw_init() argument
761 WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED || in etnaviv_gpu_hw_init()
762 gpu->state == ETNA_GPU_STATE_RESET)); in etnaviv_gpu_hw_init()
764 if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) || in etnaviv_gpu_hw_init()
765 etnaviv_is_model_rev(gpu, 0x320, 0x5220)) && in etnaviv_gpu_hw_init()
766 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { in etnaviv_gpu_hw_init()
769 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff; in etnaviv_gpu_hw_init()
771 if (gpu->identity.revision == 0x5007) in etnaviv_gpu_hw_init()
776 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); in etnaviv_gpu_hw_init()
780 etnaviv_gpu_enable_mlcg(gpu); in etnaviv_gpu_hw_init()
783 * Update GPU AXI cache atttribute to "cacheable, no allocate". in etnaviv_gpu_hw_init()
786 gpu_write(gpu, VIVS_HI_AXI_CONFIG, in etnaviv_gpu_hw_init()
791 if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) { in etnaviv_gpu_hw_init()
792 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); in etnaviv_gpu_hw_init()
797 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); in etnaviv_gpu_hw_init()
800 if (gpu->sec_mode == ETNA_SEC_KERNEL) { in etnaviv_gpu_hw_init()
801 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL); in etnaviv_gpu_hw_init()
803 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); in etnaviv_gpu_hw_init()
807 etnaviv_gpu_setup_pulse_eater(gpu); in etnaviv_gpu_hw_init()
809 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); in etnaviv_gpu_hw_init()
811 gpu->state = ETNA_GPU_STATE_INITIALIZED; in etnaviv_gpu_hw_init()
814 int etnaviv_gpu_init(struct etnaviv_gpu *gpu) in etnaviv_gpu_init() argument
816 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_init()
820 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_init()
822 dev_err(gpu->dev, "Failed to enable GPU power domain\n"); in etnaviv_gpu_init()
826 ret = etnaviv_gpu_reset_deassert(gpu); in etnaviv_gpu_init()
828 dev_err(gpu->dev, "GPU reset deassert failed\n"); in etnaviv_gpu_init()
832 etnaviv_hw_identify(gpu); in etnaviv_gpu_init()
834 if (gpu->identity.model == 0) { in etnaviv_gpu_init()
835 dev_err(gpu->dev, "Unknown GPU model\n"); in etnaviv_gpu_init()
840 if (gpu->identity.nn_core_count > 0) in etnaviv_gpu_init()
841 dev_warn(gpu->dev, "etnaviv has been instantiated on a NPU, " in etnaviv_gpu_init()
845 if (gpu->identity.features & chipFeatures_PIPE_VG && in etnaviv_gpu_init()
846 gpu->identity.features & chipFeatures_FE20) { in etnaviv_gpu_init()
847 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n"); in etnaviv_gpu_init()
856 if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) && in etnaviv_gpu_init()
857 (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB)) in etnaviv_gpu_init()
858 gpu->sec_mode = ETNA_SEC_KERNEL; in etnaviv_gpu_init()
860 gpu->state = ETNA_GPU_STATE_IDENTIFIED; in etnaviv_gpu_init()
862 ret = etnaviv_hw_reset(gpu); in etnaviv_gpu_init()
864 dev_err(gpu->dev, "GPU reset failed\n"); in etnaviv_gpu_init()
868 ret = etnaviv_iommu_global_init(gpu); in etnaviv_gpu_init()
873 ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc, &gpu->buffer, SZ_4K); in etnaviv_gpu_init()
875 dev_err(gpu->dev, "could not create command buffer\n"); in etnaviv_gpu_init()
880 * Set the GPU linear window to cover the cmdbuf region, as the GPU in etnaviv_gpu_init()
891 cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M); in etnaviv_gpu_init()
893 if (!(gpu->identity.features & chipFeatures_PIPE_3D) || in etnaviv_gpu_init()
894 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20) || in etnaviv_gpu_init()
895 (gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION)) { in etnaviv_gpu_init()
901 dev_info(gpu->dev, in etnaviv_gpu_init()
903 gpu->identity.features &= ~chipFeatures_FAST_CLEAR; in etnaviv_gpu_init()
908 spin_lock_init(&gpu->event_spinlock); in etnaviv_gpu_init()
909 init_completion(&gpu->event_free); in etnaviv_gpu_init()
910 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS); in etnaviv_gpu_init()
911 for (i = 0; i < ARRAY_SIZE(gpu->event); i++) in etnaviv_gpu_init()
912 complete(&gpu->event_free); in etnaviv_gpu_init()
915 mutex_lock(&gpu->lock); in etnaviv_gpu_init()
916 etnaviv_gpu_hw_init(gpu); in etnaviv_gpu_init()
917 mutex_unlock(&gpu->lock); in etnaviv_gpu_init()
919 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_init()
920 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_init()
925 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_init()
927 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_init()
938 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug) in verify_dma() argument
942 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in verify_dma()
943 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); in verify_dma()
946 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in verify_dma()
947 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE); in verify_dma()
957 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m) in etnaviv_gpu_debugfs() argument
963 seq_printf(m, "%s Status:\n", dev_name(gpu->dev)); in etnaviv_gpu_debugfs()
965 ret = pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_debugfs()
969 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW); in etnaviv_gpu_debugfs()
970 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH); in etnaviv_gpu_debugfs()
971 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS); in etnaviv_gpu_debugfs()
972 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_debugfs()
974 verify_dma(gpu, &debug); in etnaviv_gpu_debugfs()
977 seq_printf(m, "\t model: 0x%x\n", gpu->identity.model); in etnaviv_gpu_debugfs()
978 seq_printf(m, "\t revision: 0x%x\n", gpu->identity.revision); in etnaviv_gpu_debugfs()
979 seq_printf(m, "\t product_id: 0x%x\n", gpu->identity.product_id); in etnaviv_gpu_debugfs()
980 seq_printf(m, "\t customer_id: 0x%x\n", gpu->identity.customer_id); in etnaviv_gpu_debugfs()
981 seq_printf(m, "\t eco_id: 0x%x\n", gpu->identity.eco_id); in etnaviv_gpu_debugfs()
985 gpu->identity.features); in etnaviv_gpu_debugfs()
987 gpu->identity.minor_features0); in etnaviv_gpu_debugfs()
989 gpu->identity.minor_features1); in etnaviv_gpu_debugfs()
991 gpu->identity.minor_features2); in etnaviv_gpu_debugfs()
993 gpu->identity.minor_features3); in etnaviv_gpu_debugfs()
995 gpu->identity.minor_features4); in etnaviv_gpu_debugfs()
997 gpu->identity.minor_features5); in etnaviv_gpu_debugfs()
999 gpu->identity.minor_features6); in etnaviv_gpu_debugfs()
1001 gpu->identity.minor_features7); in etnaviv_gpu_debugfs()
1003 gpu->identity.minor_features8); in etnaviv_gpu_debugfs()
1005 gpu->identity.minor_features9); in etnaviv_gpu_debugfs()
1007 gpu->identity.minor_features10); in etnaviv_gpu_debugfs()
1009 gpu->identity.minor_features11); in etnaviv_gpu_debugfs()
1013 gpu->identity.stream_count); in etnaviv_gpu_debugfs()
1015 gpu->identity.register_max); in etnaviv_gpu_debugfs()
1017 gpu->identity.thread_count); in etnaviv_gpu_debugfs()
1019 gpu->identity.vertex_cache_size); in etnaviv_gpu_debugfs()
1021 gpu->identity.shader_core_count); in etnaviv_gpu_debugfs()
1023 gpu->identity.nn_core_count); in etnaviv_gpu_debugfs()
1025 gpu->identity.pixel_pipes); in etnaviv_gpu_debugfs()
1027 gpu->identity.vertex_output_buffer_size); in etnaviv_gpu_debugfs()
1029 gpu->identity.buffer_size); in etnaviv_gpu_debugfs()
1031 gpu->identity.instruction_count); in etnaviv_gpu_debugfs()
1033 gpu->identity.num_constants); in etnaviv_gpu_debugfs()
1035 gpu->identity.varyings_count); in etnaviv_gpu_debugfs()
1039 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP; in etnaviv_gpu_debugfs()
1081 if (gpu->identity.features & chipFeatures_DEBUG_MODE) { in etnaviv_gpu_debugfs()
1082 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0); in etnaviv_gpu_debugfs()
1083 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1); in etnaviv_gpu_debugfs()
1084 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE); in etnaviv_gpu_debugfs()
1112 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_debugfs()
1114 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_debugfs()
1122 struct etnaviv_gpu *gpu; member
1140 return dev_name(f->gpu->dev); in etnaviv_fence_get_timeline_name()
1147 return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0; in etnaviv_fence_signaled()
1164 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu) in etnaviv_gpu_fence_alloc() argument
1169 * GPU lock must already be held, otherwise fence completion order might in etnaviv_gpu_fence_alloc()
1172 lockdep_assert_held(&gpu->lock); in etnaviv_gpu_fence_alloc()
1178 f->gpu = gpu; in etnaviv_gpu_fence_alloc()
1180 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock, in etnaviv_gpu_fence_alloc()
1181 gpu->fence_context, ++gpu->next_fence); in etnaviv_gpu_fence_alloc()
1196 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events, in event_alloc() argument
1206 remaining = wait_for_completion_timeout(&gpu->event_free, timeout); in event_alloc()
1209 dev_err(gpu->dev, "wait_for_completion_timeout failed"); in event_alloc()
1218 spin_lock(&gpu->event_spinlock); in event_alloc()
1221 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS); in event_alloc()
1224 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event)); in event_alloc()
1225 set_bit(event, gpu->event_bitmap); in event_alloc()
1228 spin_unlock(&gpu->event_spinlock); in event_alloc()
1231 ret = pm_runtime_resume_and_get(gpu->dev); in event_alloc()
1241 pm_runtime_put_autosuspend(gpu->dev); in event_alloc()
1244 complete(&gpu->event_free); in event_alloc()
1249 static void event_free(struct etnaviv_gpu *gpu, unsigned int event) in event_free() argument
1251 if (!test_bit(event, gpu->event_bitmap)) { in event_free()
1252 dev_warn(gpu->dev, "event %u is already marked as free", in event_free()
1255 clear_bit(event, gpu->event_bitmap); in event_free()
1256 complete(&gpu->event_free); in event_free()
1259 pm_runtime_put_autosuspend(gpu->dev); in event_free()
1265 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu, in etnaviv_gpu_wait_fence_interruptible() argument
1277 fence = xa_load(&gpu->user_fences, id); in etnaviv_gpu_wait_fence_interruptible()
1309 * Although the retirement happens under the gpu lock, we don't want to hold
1312 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu, in etnaviv_gpu_wait_obj_inactive() argument
1324 ret = wait_event_interruptible_timeout(gpu->fence_event, in etnaviv_gpu_wait_obj_inactive()
1335 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, in sync_point_perfmon_sample() argument
1345 etnaviv_perfmon_process(gpu, pmr, submit->exec_state); in sync_point_perfmon_sample()
1349 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, in sync_point_perfmon_sample_pre() argument
1354 mutex_lock(&gpu->lock); in sync_point_perfmon_sample_pre()
1357 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); in sync_point_perfmon_sample_pre()
1359 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); in sync_point_perfmon_sample_pre()
1361 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); in sync_point_perfmon_sample_pre()
1363 mutex_unlock(&gpu->lock); in sync_point_perfmon_sample_pre()
1366 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, in sync_point_perfmon_sample_post() argument
1373 mutex_lock(&gpu->lock); in sync_point_perfmon_sample_post()
1375 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); in sync_point_perfmon_sample_post()
1378 val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS); in sync_point_perfmon_sample_post()
1380 gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val); in sync_point_perfmon_sample_post()
1382 mutex_unlock(&gpu->lock); in sync_point_perfmon_sample_post()
1392 /* add bo's to gpu's ring, and kick gpu: */
1395 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_gpu_submit() local
1402 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE in etnaviv_gpu_submit()
1404 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests in etnaviv_gpu_submit()
1410 ret = event_alloc(gpu, nr_events, event); in etnaviv_gpu_submit()
1413 pm_runtime_put_noidle(gpu->dev); in etnaviv_gpu_submit()
1417 mutex_lock(&gpu->lock); in etnaviv_gpu_submit()
1419 gpu_fence = etnaviv_gpu_fence_alloc(gpu); in etnaviv_gpu_submit()
1422 event_free(gpu, event[i]); in etnaviv_gpu_submit()
1427 if (gpu->state == ETNA_GPU_STATE_INITIALIZED) in etnaviv_gpu_submit()
1428 etnaviv_gpu_start_fe_idleloop(gpu, submit->mmu_context); in etnaviv_gpu_submit()
1432 submit->prev_mmu_context = etnaviv_iommu_context_get(gpu->mmu_context); in etnaviv_gpu_submit()
1435 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre; in etnaviv_gpu_submit()
1437 gpu->event[event[1]].submit = submit; in etnaviv_gpu_submit()
1438 etnaviv_sync_point_queue(gpu, event[1]); in etnaviv_gpu_submit()
1441 gpu->event[event[0]].fence = gpu_fence; in etnaviv_gpu_submit()
1443 etnaviv_buffer_queue(gpu, submit->exec_state, submit->mmu_context, in etnaviv_gpu_submit()
1447 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post; in etnaviv_gpu_submit()
1449 gpu->event[event[2]].submit = submit; in etnaviv_gpu_submit()
1450 etnaviv_sync_point_queue(gpu, event[2]); in etnaviv_gpu_submit()
1454 mutex_unlock(&gpu->lock); in etnaviv_gpu_submit()
1461 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu, in sync_point_worker() local
1463 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event]; in sync_point_worker()
1464 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in sync_point_worker()
1466 event->sync_point(gpu, event); in sync_point_worker()
1468 event_free(gpu, gpu->sync_point_event); in sync_point_worker()
1470 /* restart FE last to avoid GPU and IRQ racing against this worker */ in sync_point_worker()
1471 etnaviv_gpu_start_fe(gpu, addr + 2, 2); in sync_point_worker()
1476 struct etnaviv_gpu *gpu = submit->gpu; in etnaviv_gpu_recover_hang() local
1481 dev_err(gpu->dev, "recover hung GPU!\n"); in etnaviv_gpu_recover_hang()
1491 dev_err(gpu->dev, "offending task: %s (%s)\n", comm, cmd); in etnaviv_gpu_recover_hang()
1496 if (pm_runtime_get_sync(gpu->dev) < 0) in etnaviv_gpu_recover_hang()
1499 mutex_lock(&gpu->lock); in etnaviv_gpu_recover_hang()
1501 etnaviv_hw_reset(gpu); in etnaviv_gpu_recover_hang()
1503 /* complete all events, the GPU won't do it after the reset */ in etnaviv_gpu_recover_hang()
1504 spin_lock(&gpu->event_spinlock); in etnaviv_gpu_recover_hang()
1505 for_each_set_bit(i, gpu->event_bitmap, ETNA_NR_EVENTS) in etnaviv_gpu_recover_hang()
1506 event_free(gpu, i); in etnaviv_gpu_recover_hang()
1507 spin_unlock(&gpu->event_spinlock); in etnaviv_gpu_recover_hang()
1509 etnaviv_gpu_hw_init(gpu); in etnaviv_gpu_recover_hang()
1511 mutex_unlock(&gpu->lock); in etnaviv_gpu_recover_hang()
1512 pm_runtime_mark_last_busy(gpu->dev); in etnaviv_gpu_recover_hang()
1514 pm_runtime_put_autosuspend(gpu->dev); in etnaviv_gpu_recover_hang()
1517 static void dump_mmu_fault(struct etnaviv_gpu *gpu) in dump_mmu_fault() argument
1531 if (gpu->sec_mode == ETNA_SEC_NONE) in dump_mmu_fault()
1536 status = gpu_read(gpu, status_reg); in dump_mmu_fault()
1537 dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status); in dump_mmu_fault()
1551 if (gpu->sec_mode == ETNA_SEC_NONE) in dump_mmu_fault()
1556 dev_err_ratelimited(gpu->dev, in dump_mmu_fault()
1558 i, reason, gpu_read(gpu, address_reg)); in dump_mmu_fault()
1564 struct etnaviv_gpu *gpu = data; in irq_handler() local
1567 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); in irq_handler()
1573 pm_runtime_mark_last_busy(gpu->dev); in irq_handler()
1575 dev_dbg(gpu->dev, "intr 0x%08x\n", intr); in irq_handler()
1578 dev_err(gpu->dev, "AXI bus error\n"); in irq_handler()
1583 dump_mmu_fault(gpu); in irq_handler()
1584 gpu->state = ETNA_GPU_STATE_FAULT; in irq_handler()
1585 drm_sched_fault(&gpu->sched); in irq_handler()
1596 dev_dbg(gpu->dev, "event %u\n", event); in irq_handler()
1598 if (gpu->event[event].sync_point) { in irq_handler()
1599 gpu->sync_point_event = event; in irq_handler()
1600 queue_work(gpu->wq, &gpu->sync_point_work); in irq_handler()
1603 fence = gpu->event[event].fence; in irq_handler()
1607 gpu->event[event].fence = NULL; in irq_handler()
1618 if (fence_after(fence->seqno, gpu->completed_fence)) in irq_handler()
1619 gpu->completed_fence = fence->seqno; in irq_handler()
1622 event_free(gpu, event); in irq_handler()
1631 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu) in etnaviv_gpu_clk_enable() argument
1635 ret = clk_prepare_enable(gpu->clk_reg); in etnaviv_gpu_clk_enable()
1639 ret = clk_prepare_enable(gpu->clk_bus); in etnaviv_gpu_clk_enable()
1643 ret = clk_prepare_enable(gpu->clk_core); in etnaviv_gpu_clk_enable()
1647 ret = clk_prepare_enable(gpu->clk_shader); in etnaviv_gpu_clk_enable()
1654 clk_disable_unprepare(gpu->clk_core); in etnaviv_gpu_clk_enable()
1656 clk_disable_unprepare(gpu->clk_bus); in etnaviv_gpu_clk_enable()
1658 clk_disable_unprepare(gpu->clk_reg); in etnaviv_gpu_clk_enable()
1663 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu) in etnaviv_gpu_clk_disable() argument
1665 clk_disable_unprepare(gpu->clk_shader); in etnaviv_gpu_clk_disable()
1666 clk_disable_unprepare(gpu->clk_core); in etnaviv_gpu_clk_disable()
1667 clk_disable_unprepare(gpu->clk_bus); in etnaviv_gpu_clk_disable()
1668 clk_disable_unprepare(gpu->clk_reg); in etnaviv_gpu_clk_disable()
1673 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms) in etnaviv_gpu_wait_idle() argument
1678 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE); in etnaviv_gpu_wait_idle()
1680 if ((idle & gpu->idle_mask) == gpu->idle_mask) in etnaviv_gpu_wait_idle()
1684 dev_warn(gpu->dev, in etnaviv_gpu_wait_idle()
1694 static void etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu) in etnaviv_gpu_hw_suspend() argument
1696 if (gpu->state == ETNA_GPU_STATE_RUNNING) { in etnaviv_gpu_hw_suspend()
1698 mutex_lock(&gpu->lock); in etnaviv_gpu_hw_suspend()
1699 etnaviv_buffer_end(gpu); in etnaviv_gpu_hw_suspend()
1700 mutex_unlock(&gpu->lock); in etnaviv_gpu_hw_suspend()
1707 etnaviv_gpu_wait_idle(gpu, 100); in etnaviv_gpu_hw_suspend()
1709 gpu->state = ETNA_GPU_STATE_INITIALIZED; in etnaviv_gpu_hw_suspend()
1712 gpu->exec_state = -1; in etnaviv_gpu_hw_suspend()
1715 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu) in etnaviv_gpu_hw_resume() argument
1719 ret = mutex_lock_killable(&gpu->lock); in etnaviv_gpu_hw_resume()
1723 etnaviv_gpu_update_clock(gpu); in etnaviv_gpu_hw_resume()
1724 etnaviv_gpu_hw_init(gpu); in etnaviv_gpu_hw_resume()
1726 mutex_unlock(&gpu->lock); in etnaviv_gpu_hw_resume()
1744 struct etnaviv_gpu *gpu = cdev->devdata; in etnaviv_gpu_cooling_get_cur_state() local
1746 *state = gpu->freq_scale; in etnaviv_gpu_cooling_get_cur_state()
1755 struct etnaviv_gpu *gpu = cdev->devdata; in etnaviv_gpu_cooling_set_cur_state() local
1757 mutex_lock(&gpu->lock); in etnaviv_gpu_cooling_set_cur_state()
1758 gpu->freq_scale = state; in etnaviv_gpu_cooling_set_cur_state()
1759 if (!pm_runtime_suspended(gpu->dev)) in etnaviv_gpu_cooling_set_cur_state()
1760 etnaviv_gpu_update_clock(gpu); in etnaviv_gpu_cooling_set_cur_state()
1761 mutex_unlock(&gpu->lock); in etnaviv_gpu_cooling_set_cur_state()
1777 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_bind() local
1781 gpu->cooling = thermal_of_cooling_device_register(dev->of_node, in etnaviv_gpu_bind()
1782 (char *)dev_name(dev), gpu, &cooling_ops); in etnaviv_gpu_bind()
1783 if (IS_ERR(gpu->cooling)) in etnaviv_gpu_bind()
1784 return PTR_ERR(gpu->cooling); in etnaviv_gpu_bind()
1787 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0); in etnaviv_gpu_bind()
1788 if (!gpu->wq) { in etnaviv_gpu_bind()
1793 ret = etnaviv_sched_init(gpu); in etnaviv_gpu_bind()
1798 ret = etnaviv_gpu_clk_enable(gpu); in etnaviv_gpu_bind()
1803 gpu->drm = drm; in etnaviv_gpu_bind()
1804 gpu->fence_context = dma_fence_context_alloc(1); in etnaviv_gpu_bind()
1805 xa_init_flags(&gpu->user_fences, XA_FLAGS_ALLOC); in etnaviv_gpu_bind()
1806 spin_lock_init(&gpu->fence_spinlock); in etnaviv_gpu_bind()
1808 INIT_WORK(&gpu->sync_point_work, sync_point_worker); in etnaviv_gpu_bind()
1809 init_waitqueue_head(&gpu->fence_event); in etnaviv_gpu_bind()
1811 priv->gpu[priv->num_gpus++] = gpu; in etnaviv_gpu_bind()
1816 etnaviv_sched_fini(gpu); in etnaviv_gpu_bind()
1819 destroy_workqueue(gpu->wq); in etnaviv_gpu_bind()
1823 thermal_cooling_device_unregister(gpu->cooling); in etnaviv_gpu_bind()
1831 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_unbind() local
1833 DBG("%s", dev_name(gpu->dev)); in etnaviv_gpu_unbind()
1835 destroy_workqueue(gpu->wq); in etnaviv_gpu_unbind()
1837 etnaviv_sched_fini(gpu); in etnaviv_gpu_unbind()
1840 pm_runtime_get_sync(gpu->dev); in etnaviv_gpu_unbind()
1841 pm_runtime_put_sync_suspend(gpu->dev); in etnaviv_gpu_unbind()
1843 etnaviv_gpu_hw_suspend(gpu); in etnaviv_gpu_unbind()
1844 etnaviv_gpu_clk_disable(gpu); in etnaviv_gpu_unbind()
1847 if (gpu->mmu_context) in etnaviv_gpu_unbind()
1848 etnaviv_iommu_context_put(gpu->mmu_context); in etnaviv_gpu_unbind()
1850 etnaviv_cmdbuf_free(&gpu->buffer); in etnaviv_gpu_unbind()
1851 etnaviv_iommu_global_fini(gpu); in etnaviv_gpu_unbind()
1853 gpu->drm = NULL; in etnaviv_gpu_unbind()
1854 xa_destroy(&gpu->user_fences); in etnaviv_gpu_unbind()
1857 thermal_cooling_device_unregister(gpu->cooling); in etnaviv_gpu_unbind()
1858 gpu->cooling = NULL; in etnaviv_gpu_unbind()
1877 struct etnaviv_gpu *gpu; in etnaviv_gpu_platform_probe() local
1880 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL); in etnaviv_gpu_platform_probe()
1881 if (!gpu) in etnaviv_gpu_platform_probe()
1884 gpu->dev = dev; in etnaviv_gpu_platform_probe()
1885 mutex_init(&gpu->lock); in etnaviv_gpu_platform_probe()
1886 mutex_init(&gpu->sched_lock); in etnaviv_gpu_platform_probe()
1889 gpu->mmio = devm_platform_ioremap_resource(pdev, 0); in etnaviv_gpu_platform_probe()
1890 if (IS_ERR(gpu->mmio)) in etnaviv_gpu_platform_probe()
1891 return PTR_ERR(gpu->mmio); in etnaviv_gpu_platform_probe()
1895 gpu->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); in etnaviv_gpu_platform_probe()
1896 if (IS_ERR(gpu->rst)) in etnaviv_gpu_platform_probe()
1897 return dev_err_probe(dev, PTR_ERR(gpu->rst), in etnaviv_gpu_platform_probe()
1900 err = reset_control_assert(gpu->rst); in etnaviv_gpu_platform_probe()
1905 gpu->irq = platform_get_irq(pdev, 0); in etnaviv_gpu_platform_probe()
1906 if (gpu->irq < 0) in etnaviv_gpu_platform_probe()
1907 return gpu->irq; in etnaviv_gpu_platform_probe()
1909 err = devm_request_irq(dev, gpu->irq, irq_handler, 0, in etnaviv_gpu_platform_probe()
1910 dev_name(dev), gpu); in etnaviv_gpu_platform_probe()
1912 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err); in etnaviv_gpu_platform_probe()
1917 gpu->clk_reg = devm_clk_get_optional(&pdev->dev, "reg"); in etnaviv_gpu_platform_probe()
1918 DBG("clk_reg: %p", gpu->clk_reg); in etnaviv_gpu_platform_probe()
1919 if (IS_ERR(gpu->clk_reg)) in etnaviv_gpu_platform_probe()
1920 return PTR_ERR(gpu->clk_reg); in etnaviv_gpu_platform_probe()
1922 gpu->clk_bus = devm_clk_get_optional(&pdev->dev, "bus"); in etnaviv_gpu_platform_probe()
1923 DBG("clk_bus: %p", gpu->clk_bus); in etnaviv_gpu_platform_probe()
1924 if (IS_ERR(gpu->clk_bus)) in etnaviv_gpu_platform_probe()
1925 return PTR_ERR(gpu->clk_bus); in etnaviv_gpu_platform_probe()
1927 gpu->clk_core = devm_clk_get(&pdev->dev, "core"); in etnaviv_gpu_platform_probe()
1928 DBG("clk_core: %p", gpu->clk_core); in etnaviv_gpu_platform_probe()
1929 if (IS_ERR(gpu->clk_core)) in etnaviv_gpu_platform_probe()
1930 return PTR_ERR(gpu->clk_core); in etnaviv_gpu_platform_probe()
1931 gpu->base_rate_core = clk_get_rate(gpu->clk_core); in etnaviv_gpu_platform_probe()
1933 gpu->clk_shader = devm_clk_get_optional(&pdev->dev, "shader"); in etnaviv_gpu_platform_probe()
1934 DBG("clk_shader: %p", gpu->clk_shader); in etnaviv_gpu_platform_probe()
1935 if (IS_ERR(gpu->clk_shader)) in etnaviv_gpu_platform_probe()
1936 return PTR_ERR(gpu->clk_shader); in etnaviv_gpu_platform_probe()
1937 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader); in etnaviv_gpu_platform_probe()
1940 dev_set_drvdata(dev, gpu); in etnaviv_gpu_platform_probe()
1962 struct etnaviv_gpu *gpu = dev_get_drvdata(&pdev->dev); in etnaviv_gpu_platform_remove() local
1967 mutex_destroy(&gpu->lock); in etnaviv_gpu_platform_remove()
1968 mutex_destroy(&gpu->sched_lock); in etnaviv_gpu_platform_remove()
1973 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_rpm_suspend() local
1977 if (atomic_read(&gpu->sched.credit_count)) in etnaviv_gpu_rpm_suspend()
1981 mask = gpu->idle_mask & ~(VIVS_HI_IDLE_STATE_FE | in etnaviv_gpu_rpm_suspend()
1983 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask; in etnaviv_gpu_rpm_suspend()
1985 dev_warn_ratelimited(dev, "GPU not yet idle, mask: 0x%08x\n", in etnaviv_gpu_rpm_suspend()
1990 etnaviv_gpu_hw_suspend(gpu); in etnaviv_gpu_rpm_suspend()
1992 gpu->state = ETNA_GPU_STATE_IDENTIFIED; in etnaviv_gpu_rpm_suspend()
1994 return etnaviv_gpu_clk_disable(gpu); in etnaviv_gpu_rpm_suspend()
1999 struct etnaviv_gpu *gpu = dev_get_drvdata(dev); in etnaviv_gpu_rpm_resume() local
2002 ret = etnaviv_gpu_clk_enable(gpu); in etnaviv_gpu_rpm_resume()
2007 if (gpu->state == ETNA_GPU_STATE_IDENTIFIED) { in etnaviv_gpu_rpm_resume()
2008 ret = etnaviv_gpu_hw_resume(gpu); in etnaviv_gpu_rpm_resume()
2010 etnaviv_gpu_clk_disable(gpu); in etnaviv_gpu_rpm_resume()
2024 .name = "etnaviv-gpu",