Lines Matching full:gpu
17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr() argument
23 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in update_shadow_rptr()
33 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument
36 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
46 update_shadow_rptr(gpu, ring); in a5xx_flush()
63 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
66 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit_in_rb() argument
68 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_submit_in_rb()
115 a5xx_flush(gpu, ring, true); in a5xx_submit_in_rb()
116 a5xx_preempt_trigger(gpu); in a5xx_submit_in_rb()
122 a5xx_idle(gpu, ring); in a5xx_submit_in_rb()
124 msm_gpu_retire(gpu); in a5xx_submit_in_rb()
127 static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) in a5xx_submit() argument
129 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_submit()
136 a5xx_submit_in_rb(gpu, submit); in a5xx_submit()
194 update_shadow_rptr(gpu, ring); in a5xx_submit()
244 a5xx_flush(gpu, ring, false); in a5xx_submit()
247 a5xx_preempt_trigger(gpu); in a5xx_submit()
444 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state) in a5xx_set_hwcg() argument
446 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_set_hwcg()
463 gpu_write(gpu, regs[i].offset, in a5xx_set_hwcg()
467 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0); in a5xx_set_hwcg()
468 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_HYST_GPMU, state ? 0x00000004 : 0); in a5xx_set_hwcg()
471 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0); in a5xx_set_hwcg()
472 gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180); in a5xx_set_hwcg()
475 static int a5xx_me_init(struct msm_gpu *gpu) in a5xx_me_init() argument
477 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_me_init()
478 struct msm_ringbuffer *ring = gpu->rb[0]; in a5xx_me_init()
513 a5xx_flush(gpu, ring, true); in a5xx_me_init()
514 return a5xx_idle(gpu, ring) ? 0 : -EINVAL; in a5xx_me_init()
517 static int a5xx_preempt_start(struct msm_gpu *gpu) in a5xx_preempt_start() argument
519 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_preempt_start()
521 struct msm_ringbuffer *ring = gpu->rb[0]; in a5xx_preempt_start()
523 if (gpu->nr_rings == 1) in a5xx_preempt_start()
556 a5xx_flush(gpu, ring, false); in a5xx_preempt_start()
558 return a5xx_idle(gpu, ring) ? 0 : -EINVAL; in a5xx_preempt_start()
580 static int a5xx_ucode_load(struct msm_gpu *gpu) in a5xx_ucode_load() argument
582 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_ucode_load()
587 a5xx_gpu->pm4_bo = adreno_fw_create_bo(gpu, in a5xx_ucode_load()
594 DRM_DEV_ERROR(gpu->dev->dev, "could not allocate PM4: %d\n", in a5xx_ucode_load()
603 a5xx_gpu->pfp_bo = adreno_fw_create_bo(gpu, in a5xx_ucode_load()
609 DRM_DEV_ERROR(gpu->dev->dev, "could not allocate PFP: %d\n", in a5xx_ucode_load()
620 a5xx_gpu->shadow = msm_gem_kernel_new(gpu->dev, in a5xx_ucode_load()
621 sizeof(u32) * gpu->nr_rings, in a5xx_ucode_load()
623 gpu->aspace, &a5xx_gpu->shadow_bo, in a5xx_ucode_load()
631 } else if (gpu->nr_rings > 1) { in a5xx_ucode_load()
633 a5xx_preempt_fini(gpu); in a5xx_ucode_load()
634 gpu->nr_rings = 1; in a5xx_ucode_load()
642 static int a5xx_zap_shader_resume(struct msm_gpu *gpu) in a5xx_zap_shader_resume() argument
644 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_zap_shader_resume()
657 gpu->name, ret); in a5xx_zap_shader_resume()
662 static int a5xx_zap_shader_init(struct msm_gpu *gpu) in a5xx_zap_shader_init() argument
672 return a5xx_zap_shader_resume(gpu); in a5xx_zap_shader_init()
674 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); in a5xx_zap_shader_init()
693 static int a5xx_hw_init(struct msm_gpu *gpu) in a5xx_hw_init() argument
695 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_hw_init()
700 gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); in a5xx_hw_init()
704 gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); in a5xx_hw_init()
706 /* Make all blocks contribute to the GPU BUSY perf counter */ in a5xx_hw_init()
707 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF); in a5xx_hw_init()
710 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001); in a5xx_hw_init()
718 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11, in a5xx_hw_init()
720 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12, in a5xx_hw_init()
722 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13, in a5xx_hw_init()
724 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14, in a5xx_hw_init()
726 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15, in a5xx_hw_init()
728 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16, in a5xx_hw_init()
730 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17, in a5xx_hw_init()
732 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18, in a5xx_hw_init()
737 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL, in a5xx_hw_init()
741 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_CNTL, 0x01); in a5xx_hw_init()
744 gpu_write(gpu, REG_A5XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); in a5xx_hw_init()
747 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0, 6); in a5xx_hw_init()
750 gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02); in a5xx_hw_init()
753 gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, lower_32_bits(adreno_gpu->uche_trap_base)); in a5xx_hw_init()
754 gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, upper_32_bits(adreno_gpu->uche_trap_base)); in a5xx_hw_init()
755 gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, lower_32_bits(adreno_gpu->uche_trap_base)); in a5xx_hw_init()
756 gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, upper_32_bits(adreno_gpu->uche_trap_base)); in a5xx_hw_init()
758 /* Set the GMEM VA range (0 to gpu->gmem) */ in a5xx_hw_init()
759 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000); in a5xx_hw_init()
760 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000); in a5xx_hw_init()
761 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO, in a5xx_hw_init()
763 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); in a5xx_hw_init()
767 gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x20); in a5xx_hw_init()
770 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); in a5xx_hw_init()
772 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x20); in a5xx_hw_init()
773 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030); in a5xx_hw_init()
774 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x20100D0A); in a5xx_hw_init()
776 gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40); in a5xx_hw_init()
778 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40); in a5xx_hw_init()
780 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); in a5xx_hw_init()
781 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060); in a5xx_hw_init()
782 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16); in a5xx_hw_init()
787 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
791 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
794 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, in a5xx_hw_init()
798 gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); in a5xx_hw_init()
807 gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, 0, (1 << 9)); in a5xx_hw_init()
810 gpu_write(gpu, REG_A5XX_UCHE_MODE_CNTL, BIT(29)); in a5xx_hw_init()
813 gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); in a5xx_hw_init()
816 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL1, 0xA6FFFFFF); in a5xx_hw_init()
823 * CCU to be interpreted differently. This can cause gpu fault. This in a5xx_hw_init()
829 gpu_rmw(gpu, REG_A5XX_RB_DBG_ECO_CNTL, (1 << 11), 0); in a5xx_hw_init()
832 a5xx_set_hwcg(gpu, true); in a5xx_hw_init()
834 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F); in a5xx_hw_init()
839 gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, hbb << 7); in a5xx_hw_init()
840 gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, hbb << 1); in a5xx_hw_init()
844 gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, hbb); in a5xx_hw_init()
847 gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, (1 << 10)); in a5xx_hw_init()
850 gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007); in a5xx_hw_init()
853 gpu_write(gpu, REG_A5XX_CP_PROTECT(0), ADRENO_PROTECT_RW(0x04, 4)); in a5xx_hw_init()
854 gpu_write(gpu, REG_A5XX_CP_PROTECT(1), ADRENO_PROTECT_RW(0x08, 8)); in a5xx_hw_init()
855 gpu_write(gpu, REG_A5XX_CP_PROTECT(2), ADRENO_PROTECT_RW(0x10, 16)); in a5xx_hw_init()
856 gpu_write(gpu, REG_A5XX_CP_PROTECT(3), ADRENO_PROTECT_RW(0x20, 32)); in a5xx_hw_init()
857 gpu_write(gpu, REG_A5XX_CP_PROTECT(4), ADRENO_PROTECT_RW(0x40, 64)); in a5xx_hw_init()
858 gpu_write(gpu, REG_A5XX_CP_PROTECT(5), ADRENO_PROTECT_RW(0x80, 64)); in a5xx_hw_init()
861 gpu_write(gpu, REG_A5XX_CP_PROTECT(6), in a5xx_hw_init()
864 gpu_write(gpu, REG_A5XX_CP_PROTECT(7), in a5xx_hw_init()
868 gpu_write(gpu, REG_A5XX_CP_PROTECT(8), ADRENO_PROTECT_RW(0x800, 64)); in a5xx_hw_init()
869 gpu_write(gpu, REG_A5XX_CP_PROTECT(9), ADRENO_PROTECT_RW(0x840, 8)); in a5xx_hw_init()
870 gpu_write(gpu, REG_A5XX_CP_PROTECT(10), ADRENO_PROTECT_RW(0x880, 32)); in a5xx_hw_init()
871 gpu_write(gpu, REG_A5XX_CP_PROTECT(11), ADRENO_PROTECT_RW(0xAA0, 1)); in a5xx_hw_init()
874 gpu_write(gpu, REG_A5XX_CP_PROTECT(12), ADRENO_PROTECT_RW(0xCC0, 1)); in a5xx_hw_init()
875 gpu_write(gpu, REG_A5XX_CP_PROTECT(13), ADRENO_PROTECT_RW(0xCF0, 2)); in a5xx_hw_init()
878 gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8)); in a5xx_hw_init()
879 gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 16)); in a5xx_hw_init()
882 gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); in a5xx_hw_init()
885 gpu_write(gpu, REG_A5XX_CP_PROTECT(17), in a5xx_hw_init()
888 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_CNTL, 0); in a5xx_hw_init()
894 gpu_write64(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, 0x00000000); in a5xx_hw_init()
895 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); in a5xx_hw_init()
897 /* Put the GPU into 64 bit by default */ in a5xx_hw_init()
898 gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
899 gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
900 gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
901 gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
902 gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
903 gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
904 gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
905 gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
906 gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
907 gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
908 gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
909 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
917 gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, BIT(23)); in a5xx_hw_init()
918 gpu_rmw(gpu, REG_A5XX_HLSQ_DBG_ECO_CNTL, BIT(18), 0); in a5xx_hw_init()
921 ret = adreno_hw_init(gpu); in a5xx_hw_init()
926 a5xx_gpmu_ucode_init(gpu); in a5xx_hw_init()
928 gpu_write64(gpu, REG_A5XX_CP_ME_INSTR_BASE_LO, a5xx_gpu->pm4_iova); in a5xx_hw_init()
929 gpu_write64(gpu, REG_A5XX_CP_PFP_INSTR_BASE_LO, a5xx_gpu->pfp_iova); in a5xx_hw_init()
932 gpu_write64(gpu, REG_A5XX_CP_RB_BASE, gpu->rb[0]->iova); in a5xx_hw_init()
940 gpu_write(gpu, REG_A5XX_CP_RB_CNTL, in a5xx_hw_init()
945 gpu_write64(gpu, REG_A5XX_CP_RB_RPTR_ADDR, in a5xx_hw_init()
946 shadowptr(a5xx_gpu, gpu->rb[0])); in a5xx_hw_init()
949 a5xx_preempt_hw_init(gpu); in a5xx_hw_init()
952 gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK, A5XX_INT_MASK); in a5xx_hw_init()
955 gpu_write(gpu, REG_A5XX_CP_PFP_ME_CNTL, 0); in a5xx_hw_init()
956 ret = a5xx_me_init(gpu); in a5xx_hw_init()
960 ret = a5xx_power_init(gpu); in a5xx_hw_init()
969 OUT_PKT7(gpu->rb[0], CP_EVENT_WRITE, 1); in a5xx_hw_init()
970 OUT_RING(gpu->rb[0], CP_EVENT_WRITE_0_EVENT(STAT_EVENT)); in a5xx_hw_init()
972 a5xx_flush(gpu, gpu->rb[0], true); in a5xx_hw_init()
973 if (!a5xx_idle(gpu, gpu->rb[0])) in a5xx_hw_init()
985 ret = a5xx_zap_shader_init(gpu); in a5xx_hw_init()
987 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); in a5xx_hw_init()
988 OUT_RING(gpu->rb[0], 0x00000000); in a5xx_hw_init()
990 a5xx_flush(gpu, gpu->rb[0], true); in a5xx_hw_init()
991 if (!a5xx_idle(gpu, gpu->rb[0])) in a5xx_hw_init()
1000 dev_warn_once(gpu->dev->dev, in a5xx_hw_init()
1002 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0); in a5xx_hw_init()
1008 a5xx_preempt_start(gpu); in a5xx_hw_init()
1013 static void a5xx_recover(struct msm_gpu *gpu) in a5xx_recover() argument
1017 adreno_dump_info(gpu); in a5xx_recover()
1021 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i))); in a5xx_recover()
1025 a5xx_dump(gpu); in a5xx_recover()
1027 gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 1); in a5xx_recover()
1028 gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); in a5xx_recover()
1029 gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 0); in a5xx_recover()
1030 adreno_recover(gpu); in a5xx_recover()
1033 static void a5xx_destroy(struct msm_gpu *gpu) in a5xx_destroy() argument
1035 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_destroy()
1038 DBG("%s", gpu->name); in a5xx_destroy()
1040 a5xx_preempt_fini(gpu); in a5xx_destroy()
1043 msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->aspace); in a5xx_destroy()
1048 msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->aspace); in a5xx_destroy()
1053 msm_gem_unpin_iova(a5xx_gpu->gpmu_bo, gpu->aspace); in a5xx_destroy()
1058 msm_gem_unpin_iova(a5xx_gpu->shadow_bo, gpu->aspace); in a5xx_destroy()
1066 static inline bool _a5xx_check_idle(struct msm_gpu *gpu) in _a5xx_check_idle() argument
1068 if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY) in _a5xx_check_idle()
1072 * Nearly every abnormality ends up pausing the GPU and triggering a in _a5xx_check_idle()
1075 return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) & in _a5xx_check_idle()
1079 bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a5xx_idle() argument
1081 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_idle()
1090 if (!adreno_idle(gpu, ring)) in a5xx_idle()
1093 if (spin_until(_a5xx_check_idle(gpu))) { in a5xx_idle()
1094 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n", in a5xx_idle()
1095 gpu->name, __builtin_return_address(0), in a5xx_idle()
1096 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_idle()
1097 gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS), in a5xx_idle()
1098 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_idle()
1099 gpu_read(gpu, REG_A5XX_CP_RB_WPTR)); in a5xx_idle()
1108 struct msm_gpu *gpu = arg; in a5xx_fault_handler() local
1112 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(4)), in a5xx_fault_handler()
1113 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(5)), in a5xx_fault_handler()
1114 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(6)), in a5xx_fault_handler()
1115 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(7)), in a5xx_fault_handler()
1121 return adreno_fault_handler(gpu, iova, flags, info, block, scratch); in a5xx_fault_handler()
1124 static void a5xx_cp_err_irq(struct msm_gpu *gpu) in a5xx_cp_err_irq() argument
1126 u32 status = gpu_read(gpu, REG_A5XX_CP_INTERRUPT_STATUS); in a5xx_cp_err_irq()
1131 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, 0); in a5xx_cp_err_irq()
1138 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA); in a5xx_cp_err_irq()
1139 val = gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA); in a5xx_cp_err_irq()
1141 dev_err_ratelimited(gpu->dev->dev, "CP | opcode error | possible opcode=0x%8.8X\n", in a5xx_cp_err_irq()
1146 dev_err_ratelimited(gpu->dev->dev, "CP | HW fault | status=0x%8.8X\n", in a5xx_cp_err_irq()
1147 gpu_read(gpu, REG_A5XX_CP_HW_FAULT)); in a5xx_cp_err_irq()
1150 dev_err_ratelimited(gpu->dev->dev, "CP | DMA error\n"); in a5xx_cp_err_irq()
1153 u32 val = gpu_read(gpu, REG_A5XX_CP_PROTECT_STATUS); in a5xx_cp_err_irq()
1155 dev_err_ratelimited(gpu->dev->dev, in a5xx_cp_err_irq()
1162 u32 status = gpu_read(gpu, REG_A5XX_CP_AHB_FAULT); in a5xx_cp_err_irq()
1168 dev_err_ratelimited(gpu->dev->dev, in a5xx_cp_err_irq()
1175 static void a5xx_rbbm_err_irq(struct msm_gpu *gpu, u32 status) in a5xx_rbbm_err_irq() argument
1178 u32 val = gpu_read(gpu, REG_A5XX_RBBM_AHB_ERROR_STATUS); in a5xx_rbbm_err_irq()
1180 dev_err_ratelimited(gpu->dev->dev, in a5xx_rbbm_err_irq()
1187 gpu_write(gpu, REG_A5XX_RBBM_AHB_CMD, (1 << 4)); in a5xx_rbbm_err_irq()
1190 gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD, in a5xx_rbbm_err_irq()
1195 dev_err_ratelimited(gpu->dev->dev, "RBBM | AHB transfer timeout\n"); in a5xx_rbbm_err_irq()
1198 dev_err_ratelimited(gpu->dev->dev, "RBBM | ME master split | status=0x%X\n", in a5xx_rbbm_err_irq()
1199 gpu_read(gpu, REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS)); in a5xx_rbbm_err_irq()
1202 dev_err_ratelimited(gpu->dev->dev, "RBBM | PFP master split | status=0x%X\n", in a5xx_rbbm_err_irq()
1203 gpu_read(gpu, REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS)); in a5xx_rbbm_err_irq()
1206 dev_err_ratelimited(gpu->dev->dev, "RBBM | ETS master split | status=0x%X\n", in a5xx_rbbm_err_irq()
1207 gpu_read(gpu, REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS)); in a5xx_rbbm_err_irq()
1210 dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB ASYNC overflow\n"); in a5xx_rbbm_err_irq()
1213 dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB bus overflow\n"); in a5xx_rbbm_err_irq()
1216 static void a5xx_uche_err_irq(struct msm_gpu *gpu) in a5xx_uche_err_irq() argument
1218 uint64_t addr = (uint64_t) gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_HI); in a5xx_uche_err_irq()
1220 addr |= gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_LO); in a5xx_uche_err_irq()
1222 dev_err_ratelimited(gpu->dev->dev, "UCHE | Out of bounds access | addr=0x%llX\n", in a5xx_uche_err_irq()
1226 static void a5xx_gpmu_err_irq(struct msm_gpu *gpu) in a5xx_gpmu_err_irq() argument
1228 dev_err_ratelimited(gpu->dev->dev, "GPMU | voltage droop\n"); in a5xx_gpmu_err_irq()
1231 static void a5xx_fault_detect_irq(struct msm_gpu *gpu) in a5xx_fault_detect_irq() argument
1233 struct drm_device *dev = gpu->dev; in a5xx_fault_detect_irq()
1234 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); in a5xx_fault_detect_irq()
1237 * If stalled on SMMU fault, we could trip the GPU's hang detection, in a5xx_fault_detect_irq()
1242 if (gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24)) in a5xx_fault_detect_irq()
1245 …DRM_DEV_ERROR(dev->dev, "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4… in a5xx_fault_detect_irq()
1247 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_fault_detect_irq()
1248 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_fault_detect_irq()
1249 gpu_read(gpu, REG_A5XX_CP_RB_WPTR), in a5xx_fault_detect_irq()
1250 gpu_read64(gpu, REG_A5XX_CP_IB1_BASE), in a5xx_fault_detect_irq()
1251 gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ), in a5xx_fault_detect_irq()
1252 gpu_read64(gpu, REG_A5XX_CP_IB2_BASE), in a5xx_fault_detect_irq()
1253 gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ)); in a5xx_fault_detect_irq()
1256 del_timer(&gpu->hangcheck_timer); in a5xx_fault_detect_irq()
1258 kthread_queue_work(gpu->worker, &gpu->recover_work); in a5xx_fault_detect_irq()
1269 static irqreturn_t a5xx_irq(struct msm_gpu *gpu) in a5xx_irq() argument
1271 struct msm_drm_private *priv = gpu->dev->dev_private; in a5xx_irq()
1272 u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS); in a5xx_irq()
1278 gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD, in a5xx_irq()
1288 a5xx_rbbm_err_irq(gpu, status); in a5xx_irq()
1291 a5xx_cp_err_irq(gpu); in a5xx_irq()
1294 a5xx_fault_detect_irq(gpu); in a5xx_irq()
1297 a5xx_uche_err_irq(gpu); in a5xx_irq()
1300 a5xx_gpmu_err_irq(gpu); in a5xx_irq()
1303 a5xx_preempt_trigger(gpu); in a5xx_irq()
1304 msm_gpu_retire(gpu); in a5xx_irq()
1308 a5xx_preempt_irq(gpu); in a5xx_irq()
1344 static void a5xx_dump(struct msm_gpu *gpu) in a5xx_dump() argument
1346 DRM_DEV_INFO(gpu->dev->dev, "status: %08x\n", in a5xx_dump()
1347 gpu_read(gpu, REG_A5XX_RBBM_STATUS)); in a5xx_dump()
1348 adreno_dump(gpu); in a5xx_dump()
1351 static int a5xx_pm_resume(struct msm_gpu *gpu) in a5xx_pm_resume() argument
1353 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_pm_resume()
1357 ret = msm_gpu_pm_resume(gpu); in a5xx_pm_resume()
1364 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0x00000055); in a5xx_pm_resume()
1365 a5xx_set_hwcg(gpu, true); in a5xx_pm_resume()
1367 gpu_rmw(gpu, REG_A5XX_RBBM_CLOCK_CNTL, 0xff, 0); in a5xx_pm_resume()
1372 gpu_write(gpu, REG_A5XX_GPMU_RBCCU_POWER_CNTL, 0x778000); in a5xx_pm_resume()
1377 ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS, in a5xx_pm_resume()
1381 gpu->name, in a5xx_pm_resume()
1382 gpu_read(gpu, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS)); in a5xx_pm_resume()
1387 gpu_write(gpu, REG_A5XX_GPMU_SP_POWER_CNTL, 0x778000); in a5xx_pm_resume()
1388 ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_SP_PWR_CLK_STATUS, in a5xx_pm_resume()
1392 gpu->name); in a5xx_pm_resume()
1397 static int a5xx_pm_suspend(struct msm_gpu *gpu) in a5xx_pm_suspend() argument
1399 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_pm_suspend()
1410 gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, mask); in a5xx_pm_suspend()
1411 spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) & in a5xx_pm_suspend()
1414 gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0); in a5xx_pm_suspend()
1421 gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000); in a5xx_pm_suspend()
1422 gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000); in a5xx_pm_suspend()
1425 ret = msm_gpu_pm_suspend(gpu); in a5xx_pm_suspend()
1430 for (i = 0; i < gpu->nr_rings; i++) in a5xx_pm_suspend()
1436 static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) in a5xx_get_timestamp() argument
1438 *value = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO); in a5xx_get_timestamp()
1454 static int a5xx_crashdumper_init(struct msm_gpu *gpu, in a5xx_crashdumper_init() argument
1457 dumper->ptr = msm_gem_kernel_new(gpu->dev, in a5xx_crashdumper_init()
1458 SZ_1M, MSM_BO_WC, gpu->aspace, in a5xx_crashdumper_init()
1467 static int a5xx_crashdumper_run(struct msm_gpu *gpu, in a5xx_crashdumper_run() argument
1475 gpu_write64(gpu, REG_A5XX_CP_CRASH_SCRIPT_BASE_LO, dumper->iova); in a5xx_crashdumper_run()
1477 gpu_write(gpu, REG_A5XX_CP_CRASH_DUMP_CNTL, 1); in a5xx_crashdumper_run()
1479 return gpu_poll_timeout(gpu, REG_A5XX_CP_CRASH_DUMP_CNTL, val, in a5xx_crashdumper_run()
1510 static void a5xx_gpu_state_get_hlsq_regs(struct msm_gpu *gpu, in a5xx_gpu_state_get_hlsq_regs() argument
1518 if (a5xx_crashdumper_init(gpu, &dumper)) in a5xx_gpu_state_get_hlsq_regs()
1556 if (a5xx_crashdumper_run(gpu, &dumper)) { in a5xx_gpu_state_get_hlsq_regs()
1558 msm_gem_kernel_put(dumper.bo, gpu->aspace); in a5xx_gpu_state_get_hlsq_regs()
1566 msm_gem_kernel_put(dumper.bo, gpu->aspace); in a5xx_gpu_state_get_hlsq_regs()
1569 static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu) in a5xx_gpu_state_get() argument
1573 bool stalled = !!(gpu_read(gpu, REG_A5XX_RBBM_STATUS3) & BIT(24)); in a5xx_gpu_state_get()
1579 a5xx_set_hwcg(gpu, false); in a5xx_gpu_state_get()
1582 adreno_gpu_state_get(gpu, &(a5xx_state->base)); in a5xx_gpu_state_get()
1584 a5xx_state->base.rbbm_status = gpu_read(gpu, REG_A5XX_RBBM_STATUS); in a5xx_gpu_state_get()
1592 a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state); in a5xx_gpu_state_get()
1594 a5xx_set_hwcg(gpu, true); in a5xx_gpu_state_get()
1622 static void a5xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, in a5xx_show() argument
1633 adreno_show(gpu, state, p); in a5xx_show()
1663 static struct msm_ringbuffer *a5xx_active_ring(struct msm_gpu *gpu) in a5xx_active_ring() argument
1665 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_active_ring()
1671 static u64 a5xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) in a5xx_gpu_busy() argument
1675 busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO); in a5xx_gpu_busy()
1676 *out_sample_rate = clk_get_rate(gpu->core_clk); in a5xx_gpu_busy()
1681 static uint32_t a5xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a5xx_get_rptr() argument
1683 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_get_rptr()
1689 return ring->memptrs->rptr = gpu_read(gpu, REG_A5XX_CP_RB_RPTR); in a5xx_get_rptr()
1759 struct msm_gpu *gpu; in a5xx_gpu_init() local
1768 gpu = &adreno_gpu->base; in a5xx_gpu_init()
1787 if (gpu->aspace) in a5xx_gpu_init()
1788 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a5xx_fault_handler); in a5xx_gpu_init()
1791 a5xx_preempt_init(gpu); in a5xx_gpu_init()
1805 return gpu; in a5xx_gpu_init()