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/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_gpt.c8 * This file is a driver for the General Purpose Timer (gpt) devices
14 * This driver supports the GPIO and IRQ controller functions of the GPT
18 * this prevents the use of any gpt0 gpt function (i.e. they will fail with
19 * -EBUSY). Thus, the safety wdt function always has precedence over the gpt
25 * to the device tree node for the gpt device (typically in the .dts file
33 * be added to the device tree node for the gpt device:
38 * the IRQ number because the GPT only has a single IRQ source. For flags,
72 MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
77 * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
79 * @regs: virtual address of GPT registers
[all …]
H A DKconfig20 gpt nodes, then it is safe to use such gpt to reset the board,
H A Dmpc5200_simple.c16 * gpt nodes, then it is safe to use such gpt to reset the board,
/linux/block/partitions/
H A Defi.c19 * AGPT, allow override with 'gpt' kernel command line option.
40 * - moved le_efi_guid_to_cpus() back into this file. GPT is the only
42 * - Changed gpt structure names and members to be simpler and more Linux-like.
64 * - Added kernel command line option 'gpt' to override valid PMBR test.
93 /* This allows a kernel command line option 'gpt' to override
104 __setup("gpt", force_gpt_fn);
145 /* set to 0x00000001 (i.e., the LBA of the GPT Partition Header) */ in pmbr_part_valid()
167 * marked out by up to three GPT partitions.
217 pr_debug("GPT: mbr size in lba (%u) different than whole disk (%u).\n", in is_pmbr_valid()
265 * @gpt: GPT header
[all …]
/linux/drivers/clk/spear/
H A Dclk-gpt-synth.c9 #define pr_fmt(fmt) "clk-gpt-synth: " fmt
24 * Calculates gpt synth clk rate for different values of mscale and nscale
34 struct clk_gpt *gpt = to_clk_gpt(hw); in gpt_calc_rate() local
35 struct gpt_rate_tbl *rtbl = gpt->rtbl; in gpt_calc_rate()
45 struct clk_gpt *gpt = to_clk_gpt(hw); in clk_gpt_determine_rate() local
49 gpt_calc_rate, gpt->rtbl_cnt, &unused); in clk_gpt_determine_rate()
57 struct clk_gpt *gpt = to_clk_gpt(hw); in clk_gpt_recalc_rate() local
61 if (gpt->lock) in clk_gpt_recalc_rate()
62 spin_lock_irqsave(gpt->lock, flags); in clk_gpt_recalc_rate()
64 val = readl_relaxed(gpt->reg); in clk_gpt_recalc_rate()
[all …]
H A DMakefile6 obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
/linux/drivers/clocksource/
H A Dtimer-imx-gpt.c73 const struct imx_gpt_data *gpt; member
155 void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn; in mxc_clocksource_init()
206 /* Disable interrupt in GPT module */ in mxc_shutdown()
207 imxtm->gpt->gpt_irq_disable(imxtm); in mxc_shutdown()
209 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); in mxc_shutdown()
211 writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp); in mxc_shutdown()
214 imxtm->gpt->gpt_irq_acknowledge(imxtm); in mxc_shutdown()
227 /* Disable interrupt in GPT module */ in mxc_set_oneshot()
228 imxtm->gpt->gpt_irq_disable(imxtm); in mxc_set_oneshot()
231 u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn); in mxc_set_oneshot()
[all …]
H A Dtimer-pistachio.c112 /* Disable GPT local before loading reload value */ in pistachio_clksrc_enable()
120 /* Disable GPT local */ in pistachio_clksrc_disable()
/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rzg2l-poeg.yaml7 title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
13 The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT) can be
14 disabled by using the port output enabling function for the GPT (POEG).
17 * Output-disable request from the GPT.
21 are controlled by the GPT module.
46 renesas,gpt:
48 description: phandle to gpt instance that serves the pwm operation.
68 - renesas,gpt
85 renesas,gpt = <&gpt>;
H A Dlantiq,pinctrl-xway.txt51 spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
62 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
74 spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe
89 spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy
/linux/arch/powerpc/boot/dts/
H A Dmpc5200b.dtsi64 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
72 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
79 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
86 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
93 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
100 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
107 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
114 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
H A Dlite5200.dts63 compatible = "fsl,mpc5200-gpt";
70 compatible = "fsl,mpc5200-gpt";
76 compatible = "fsl,mpc5200-gpt";
82 compatible = "fsl,mpc5200-gpt";
88 compatible = "fsl,mpc5200-gpt";
94 compatible = "fsl,mpc5200-gpt";
100 compatible = "fsl,mpc5200-gpt";
106 compatible = "fsl,mpc5200-gpt";
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc5200.txt84 timer@<addr> fsl,mpc5200-gpt General purpose timers
102 fsl,mpc5200-gpt nodes
107 the watchdog. The timer will function as a GPT if the timer api is used, and
109 mode has priority over the gpt mode, i.e. if the watchdog is activated, any
110 gpt api call to this timer will fail with -EBUSY.
114 GPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it.
117 - just mark GPT0 as watchdog, blocking gpt accesses, and configure it later;
123 An mpc5200-gpt can be used as a single line GPIO controller. To do so,
124 add the following properties to the gpt node:
131 An mpc5200-gpt can be used as a single line edge sensitive interrupt
[all …]
/linux/Documentation/devicetree/bindings/pwm/
H A Drenesas,rzg2l-gpt.yaml4 $id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml#
7 title: Renesas RZ/G2L General PWM Timer (GPT)
13 RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer
63 - renesas,r9a07g044-gpt # RZ/G2{L,LC}
64 - renesas,r9a07g054-gpt # RZ/V2L
65 - const: renesas,rzg2l-gpt
267 gpt: pwm@10048000 {
268 compatible = "renesas,r9a07g044-gpt", "renesas,rzg2l-gpt";
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27.dtsi110 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
119 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
128 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
387 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
396 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
447 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
H A Dimxrt1050.dtsi152 gpt: timer@401ec000 { label
153 compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt";
H A Dimx25.dtsi362 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
370 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
378 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
386 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
H A Dimx7s.dtsi497 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
506 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
516 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
526 compatible = "fsl,imx7d-gpt", "fsl,imx6dl-gpt";
/linux/drivers/pwm/
H A Dpwm-rzg2l-gpt.c3 * Renesas RZ/G2L General PWM Timer (GPT) driver
15 * - General PWM Timer (GPT) has 8 HW channels for PWM operations and
269 * GPT counter is shared by the two IOs of a single channel, so in rzg2l_gpt_config()
289 * GPT counter is shared by multiple channels, we cache the period ticks in rzg2l_gpt_config()
304 /* GPT set operating mode (saw-wave up-counting) */ in rzg2l_gpt_config()
402 return dev_err_probe(dev, -EINVAL, "The gpt clk rate is 0"); in rzg2l_gpt_probe()
409 return dev_err_probe(dev, -EINVAL, "The gpt clk rate is > 1GHz"); in rzg2l_gpt_probe()
431 { .compatible = "renesas,rzg2l-gpt", },
438 .name = "pwm-rzg2l-gpt",
446 MODULE_DESCRIPTION("Renesas RZ/G2L General PWM Timer (GPT) Driver");
/linux/drivers/gpu/drm/i915/gvt/
H A Dtrace.h191 TP_PROTO(int id, const char *tag, int page_id, void *gpt, int type),
193 TP_ARGS(id, tag, page_id, gpt, type),
201 "VM%d [oos %s] page id %d gpt %p type %d\n",
202 id, tag, page_id, gpt, type);
209 TP_PROTO(int id, int page_id, void *gpt, int type, u64 v,
212 TP_ARGS(id, page_id, gpt, type, v, index),
220 "VM%d [oos sync] page id %d gpt %p type %d entry 0x%llx index 0x%lx\n",
221 id, page_id, gpt, type, v, index);
/linux/drivers/pinctrl/
H A Dpinctrl-xway.c119 MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
120 MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT),
140 MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT),
195 GRP_MUX("gpt1", GPT, ase_pins_gpt1),
196 GRP_MUX("gpt2", GPT, ase_pins_gpt2),
197 GRP_MUX("gpt3", GPT, ase_pins_gpt3),
232 {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)},
249 MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
264 MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
271 MFP_XWAY(GPIO28, GPIO, GPT, MII, SDIO),
[all …]
/linux/arch/arm/mach-spear/
H A Dspear3xx.c81 pr_err("%s:couldn't get clk for gpt\n", __func__); in spear3xx_timer_init()
88 pr_err("%s:couldn't get %s as parent for gpt\n", in spear3xx_timer_init()
H A Dtime.c27 * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
229 pr_err("%s:couldn't get clk for gpt\n", __func__); in spear_setup_of_timer()
235 pr_err("%s:couldn't prepare-enable gpt clock\n", __func__); in spear_setup_of_timer()
H A Dspear13xx.c108 pr_err("%s:couldn't get clk for gpt\n", __func__); in spear13xx_timer_init()
115 pr_err("%s:couldn't get %s as parent for gpt\n", __func__, in spear13xx_timer_init()
/linux/arch/powerpc/include/asm/
H A Dmpc52xx.h106 /* GPT */
283 extern int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
285 extern u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt);
286 extern int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt);

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